[llvm] r254911 - [mips][ias] Removed DSP/DSPr2 instructions from base architecture valid-xfail.s's.
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 7 06:12:46 PST 2015
Author: dsanders
Date: Mon Dec 7 08:12:44 2015
New Revision: 254911
URL: http://llvm.org/viewvc/llvm-project?rev=254911&view=rev
Log:
[mips][ias] Removed DSP/DSPr2 instructions from base architecture valid-xfail.s's.
Summary:
valid-xfail.s is for instructions that should be valid in the given ISA but
incorrectly fail. DSP/DSPr2 instructions are correct to fail since DSP/DSPr2 is
not enabled.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D15072
Added:
llvm/trunk/test/MC/Mips/mips32r2/invalid-dsp.s
llvm/trunk/test/MC/Mips/mips32r2/invalid-dspr2.s
Modified:
llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s
llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s
llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s
llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s
Added: llvm/trunk/test/MC/Mips/mips32r2/invalid-dsp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/invalid-dsp.s?rev=254911&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/invalid-dsp.s (added)
+++ llvm/trunk/test/MC/Mips/mips32r2/invalid-dsp.s Mon Dec 7 08:12:44 2015
@@ -0,0 +1,97 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding \
+# RUN: -mcpu=mips32r2 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addu.qb $s6,$v1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addu_s.qb $s4,$s8,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addwc $k0,$s6,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bitrev $14,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmp.eq.ph $s7,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmp.le.ph $8,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmp.lt.ph $k0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpgu.eq.qb $14,$s6,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpgu.le.qb $9,$a3,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpgu.lt.qb $sp,$at,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpu.eq.qb $v0,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpu.le.qb $s1,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpu.lt.qb $at,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpaq_sa.l.w $ac0,$a2,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpau.h.qbl $ac1,$10,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpau.h.qbr $ac1,$s7,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpsq_s.w.ph $ac0,$gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpsq_sa.l.w $ac0,$a3,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpsu.h.qbl $ac2,$14,$10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpsu.h.qbr $ac2,$a1,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extpdpv $s6,$ac0,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extpv $13,$ac0,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extrv.w $8,$ac3,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extrv_r.w $8,$ac1,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extrv_rs.w $gp,$ac1,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extrv_s.h $s2,$ac1,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ insv $s2,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ lbux $9,$14($v0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ lhx $sp,$k0($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ lwx $12,$12($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ madd $ac2,$sp,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ maddu $ac2,$a1,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ maq_s.w.phl $ac2,$25,$11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ maq_s.w.phr $ac0,$10,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ maq_sa.w.phl $ac3,$a1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ maq_sa.w.phr $ac1,$at,$10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mfhi $9,$ac2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mflo $9,$ac2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ modsub $a3,$12,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mthi $v0,$ac1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mthlip $a3,$ac0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mtlo $v0,$ac1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ muleq_s.w.phl $11,$s4,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ muleq_s.w.phr $s6,$a0,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ muleu_s.ph.qbl $a2,$14,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ muleu_s.ph.qbr $a1,$ra,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mulq_rs.ph $s2,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mulsaq_s.w.ph $ac0,$ra,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mult $ac1, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ multu $ac1, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ packrl.ph $ra,$24,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pick.ph $ra,$a2,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pick.qb $11,$a0,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precequ.ph.qbl $s7,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precequ.ph.qbla $a0,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precequ.ph.qbr $ra,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precequ.ph.qbra $24,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ preceu.ph.qbl $sp,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ preceu.ph.qbla $s6,$11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ preceu.ph.qbr $gp,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ preceu.ph.qbra $k1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precrq.ph.w $14,$s8,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precrq.qb.ph $a2,$12,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precrq_rs.ph.w $a1,$k0,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precrqu_s.qb.ph $zero,$gp,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ raddu.w.qb $25,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ repl.ph $at,-307 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ replv.ph $v1,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ replv.qb $25,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shilo $ac1,26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shilov $ac2,$10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shllv.ph $10,$s0,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shllv.qb $gp,$v1,$zero # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shllv_s.ph $k1,$at,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shllv_s.w $s1,$ra,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shrav.ph $25,$s2,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shrav_r.ph $s3,$11,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shrav_r.w $s7,$s4,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shrlv.qb $a2,$s2,$11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subq.ph $ra,$9,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subq_s.ph $13,$s8,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subq_s.w $k1,$a2,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subu.qb $s6,$a2,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subu_s.qb $s1,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Added: llvm/trunk/test/MC/Mips/mips32r2/invalid-dspr2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/invalid-dspr2.s?rev=254911&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/invalid-dspr2.s (added)
+++ llvm/trunk/test/MC/Mips/mips32r2/invalid-dspr2.s Mon Dec 7 08:12:44 2015
@@ -0,0 +1,134 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding \
+# RUN: -mcpu=mips32r2 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ absq_s.qb $15,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addqh.ph $s4,$14,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addqh_r.ph $sp,$25,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addu.ph $a2,$14,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addu.qb $s6,$v1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addu_s.ph $a3,$s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addu_s.qb $s4,$s8,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ adduh.qb $a1,$a1,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ adduh_r.qb $a0,$9,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ addwc $k0,$s6,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ bitrev $14,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmp.eq.ph $s7,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmp.le.ph $8,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmp.lt.ph $k0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpgdu.eq.qb $s3,$zero,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpgdu.le.qb $v1,$15,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpgdu.lt.qb $s0,$gp,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpgu.eq.qb $14,$s6,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpgu.le.qb $9,$a3,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpgu.lt.qb $sp,$at,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpu.eq.qb $v0,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpu.le.qb $s1,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ cmpu.lt.qb $at,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpa.w.ph $ac1,$s7,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpaq_sa.l.w $ac0,$a2,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpaqx_s.w.ph $ac3,$a0,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpaqx_sa.w.ph $ac1,$zero,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpau.h.qbl $ac1,$10,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpau.h.qbr $ac1,$s7,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpax.w.ph $ac3,$a0,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dps.w.ph $ac1,$a3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpsq_s.w.ph $ac0,$gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpsq_sa.l.w $ac0,$a3,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpsqx_s.w.ph $ac3,$13,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpsqx_sa.w.ph $ac3,$sp,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpsu.h.qbl $ac2,$14,$10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpsu.h.qbr $ac2,$a1,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ dpsx.w.ph $ac0,$s7,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extpdpv $s6,$ac0,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extpv $13,$ac0,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extrv.w $8,$ac3,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extrv_r.w $8,$ac1,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extrv_rs.w $gp,$ac1,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ extrv_s.h $s2,$ac1,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ insv $s2,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ lbux $9,$14($v0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ lhx $sp,$k0($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ lwx $12,$12($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ madd $ac2,$sp,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ maddu $ac2,$a1,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ maq_s.w.phl $ac2,$25,$11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ maq_s.w.phr $ac0,$10,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ maq_sa.w.phl $ac3,$a1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ maq_sa.w.phr $ac1,$at,$10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mfhi $9,$ac2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mflo $9,$ac2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ modsub $a3,$12,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mthi $v0,$ac1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mthlip $a3,$ac0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mtlo $v0,$ac1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mul.ph $10,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mul.ph $s4,$24,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mul_s.ph $10,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ muleq_s.w.phl $11,$s4,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ muleq_s.w.phr $s6,$a0,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ muleu_s.ph.qbl $a2,$14,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ muleu_s.ph.qbr $a1,$ra,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mulq_rs.ph $s2,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mulq_rs.w $at,$s4,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mulq_s.ph $s0,$k1,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mulq_s.w $9,$a3,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mulsa.w.ph $ac1,$s4,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mulsaq_s.w.ph $ac0,$ra,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ mult $ac1, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ multu $ac1, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ packrl.ph $ra,$24,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pick.ph $ra,$a2,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ pick.qb $11,$a0,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precequ.ph.qbl $s7,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precequ.ph.qbla $a0,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precequ.ph.qbr $ra,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precequ.ph.qbra $24,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ preceu.ph.qbl $sp,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ preceu.ph.qbla $s6,$11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ preceu.ph.qbr $gp,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ preceu.ph.qbra $k1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precr.qb.ph $v0,$12,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precrq.ph.w $14,$s8,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precrq.qb.ph $a2,$12,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precrq_rs.ph.w $a1,$k0,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ precrqu_s.qb.ph $zero,$gp,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ raddu.w.qb $25,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ repl.ph $at,-307 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ replv.ph $v1,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ replv.qb $25,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shilo $ac1,26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shilov $ac2,$10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shllv.ph $10,$s0,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shllv.qb $gp,$v1,$zero # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shllv_s.ph $k1,$at,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shllv_s.w $s1,$ra,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shrav.ph $25,$s2,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shrav.qb $zero,$24,$11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shrav_r.ph $s3,$11,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shrav_r.qb $a0,$sp,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shrav_r.w $s7,$s4,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shrlv.ph $14,$10,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ shrlv.qb $a2,$s2,$11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subq.ph $ra,$9,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subq_s.ph $13,$s8,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subq_s.w $k1,$a2,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subqh.ph $10,$at,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subqh.w $v0,$a2,$zero # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subqh_r.ph $a0,$12,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subqh_r.w $10,$a2,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subu.ph $9,$s6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subu.qb $s6,$a2,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subu_s.ph $v1,$a1,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subu_s.qb $s1,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subuh.qb $zero,$gp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ subuh_r.qb $s4,$s8,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s?rev=254911&r1=254910&r2=254911&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s Mon Dec 7 08:12:44 2015
@@ -8,27 +8,10 @@
.set noat
abs.ps $f22,$f8
- absq_s.ph $8,$a0
- absq_s.qb $15,$s1
- absq_s.w $s3,$ra
add.ps $f25,$f27,$f13
- addq.ph $s1,$15,$at
- addq_s.ph $s3,$s6,$s2
- addq_s.w $a2,$8,$at
- addqh.ph $s4,$14,$s1
addqh.w $s7,$s7,$k1
- addqh_r.ph $sp,$25,$s8
addqh_r.w $8,$v1,$zero
- addsc $s8,$15,$12
- addu.ph $a2,$14,$s3
- addu.qb $s6,$v1,$v1
- addu_s.ph $a3,$s3,$gp
- addu_s.qb $s4,$s8,$s1
- adduh.qb $a1,$a1,$at
- adduh_r.qb $a0,$9,$12
- addwc $k0,$s6,$s7
alnv.ps $f12,$f18,$f30,$12
- bitrev $14,$at
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -76,18 +59,6 @@
ceil.l.d $f1,$f3
ceil.l.s $f18,$f13
cfcmsa $s6,$19
- cmp.eq.ph $s7,$14
- cmp.le.ph $8,$14
- cmp.lt.ph $k0,$sp
- cmpgdu.eq.qb $s3,$zero,$k0
- cmpgdu.le.qb $v1,$15,$s2
- cmpgdu.lt.qb $s0,$gp,$sp
- cmpgu.eq.qb $14,$s6,$s8
- cmpgu.le.qb $9,$a3,$s4
- cmpgu.lt.qb $sp,$at,$8
- cmpu.eq.qb $v0,$24
- cmpu.le.qb $s1,$a1
- cmpu.lt.qb $at,$a3
ctcmsa $31,$s7
cvt.d.l $f4,$f16
cvt.ps.s $f3,$f18,$f19
@@ -95,112 +66,44 @@
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmt $k0
- dpa.w.ph $ac1,$s7,$k0
- dpaq_s.w.ph $ac2,$a0,$13
- dpaq_sa.l.w $ac0,$a2,$14
- dpaqx_s.w.ph $ac3,$a0,$24
- dpaqx_sa.w.ph $ac1,$zero,$s5
- dpau.h.qbl $ac1,$10,$24
- dpau.h.qbr $ac1,$s7,$s6
- dpax.w.ph $ac3,$a0,$k0
- dps.w.ph $ac1,$a3,$a1
- dpsq_s.w.ph $ac0,$gp,$k0
- dpsq_sa.l.w $ac0,$a3,$15
- dpsqx_s.w.ph $ac3,$13,$a3
- dpsqx_sa.w.ph $ac3,$sp,$s2
- dpsu.h.qbl $ac2,$14,$10
- dpsu.h.qbr $ac2,$a1,$s6
- dpsx.w.ph $ac0,$s7,$gp
dvpe $s6
emt $8
evpe $v0
- extpdpv $s6,$ac0,$s8
- extpv $13,$ac0,$14
- extrv.w $8,$ac3,$at
- extrv_r.w $8,$ac1,$s6
- extrv_rs.w $gp,$ac1,$s6
- extrv_s.h $s2,$ac1,$14
floor.l.d $f26,$f7
floor.l.s $f12,$f5
fork $s2,$8,$a0
- insv $s2,$at
iret
lbe $14,122($9)
lbue $11,-108($10)
- lbux $9,$14($v0)
lhe $s6,219($v1)
lhue $gp,118($11)
- lhx $sp,$k0($15)
lle $gp,-237($ra)
lwe $ra,-145($14)
lwle $11,-42($11)
lwre $sp,-152($24)
- lwx $12,$12($s4)
madd.ps $f22,$f3,$f14,$f3
- maq_s.w.phl $ac2,$25,$11
- maq_s.w.phr $ac0,$10,$25
- maq_sa.w.phl $ac3,$a1,$v1
- maq_sa.w.phr $ac1,$at,$10
mfgc0 $s6,c0_datahi1
- mflo $9,$ac2
- modsub $a3,$12,$a3
mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
movt.ps $f20,$f25,$fcc2
movz.ps $f18,$f17,$ra
- msub $ac2,$sp,$14
msub.ps $f12,$f14,$f29,$f17
- msubu $ac2,$a1,$24
mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7
- mthi $v0,$ac1
- mthlip $a3,$ac0
- mul.ph $s4,$24,$s0
mul.ps $f14,$f0,$f16
- mul_s.ph $10,$14,$15
- muleq_s.w.phl $11,$s4,$s4
- muleq_s.w.phr $s6,$a0,$s8
- muleu_s.ph.qbl $a2,$14,$8
- muleu_s.ph.qbr $a1,$ra,$9
- mulq_rs.ph $s2,$14,$15
- mulq_rs.w $at,$s4,$25
- mulq_s.ph $s0,$k1,$15
- mulq_s.w $9,$a3,$s0
- mulsa.w.ph $ac1,$s4,$s6
- mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- packrl.ph $ra,$24,$14
- pick.ph $ra,$a2,$gp
- pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15
- precequ.ph.qbl $s7,$ra
- precequ.ph.qbla $a0,$9
- precequ.ph.qbr $ra,$s3
- precequ.ph.qbra $24,$8
- preceu.ph.qbl $sp,$8
- preceu.ph.qbla $s6,$11
- preceu.ph.qbr $gp,$s1
- preceu.ph.qbra $k1,$s0
- precr.qb.ph $v0,$12,$s8
- precrq.ph.w $14,$s8,$24
- precrq.qb.ph $a2,$12,$12
- precrq_rs.ph.w $a1,$k0,$a3
- precrqu_s.qb.ph $zero,$gp,$s5
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
- raddu.w.qb $25,$s3
rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
- repl.ph $at,-307
- replv.ph $v1,$s7
- replv.qb $25,$12
rorv $13,$a3,$s5
round.l.d $f12,$f1
round.l.s $f25,$f5
@@ -209,33 +112,7 @@
sbe $s7,33($s1)
sce $sp,189($10)
she $24,105($v0)
- shilo $ac1,26
- shilov $ac2,$10
- shllv.ph $10,$s0,$s0
- shllv.qb $gp,$v1,$zero
- shllv_s.ph $k1,$at,$13
- shllv_s.w $s1,$ra,$k0
- shrav.ph $25,$s2,$s1
- shrav.qb $zero,$24,$11
- shrav_r.ph $s3,$11,$25
- shrav_r.qb $a0,$sp,$s5
- shrav_r.w $s7,$s4,$s6
- shrlv.ph $14,$10,$9
- shrlv.qb $a2,$s2,$11
sub.ps $f5,$f14,$f26
- subq.ph $ra,$9,$s8
- subq_s.ph $13,$s8,$s5
- subq_s.w $k1,$a2,$a3
- subqh.ph $10,$at,$9
- subqh.w $v0,$a2,$zero
- subqh_r.ph $a0,$12,$s6
- subqh_r.w $10,$a2,$gp
- subu.ph $9,$s6,$s4
- subu.qb $s6,$a2,$s6
- subu_s.ph $v1,$a1,$s3
- subu_s.qb $s1,$at,$ra
- subuh.qb $zero,$gp,$gp
- subuh_r.qb $s4,$s8,$s6
swe $24,94($k0)
swle $v1,-209($gp)
swre $k0,-202($s2)
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s?rev=254911&r1=254910&r2=254911&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid-xfail.s Mon Dec 7 08:12:44 2015
@@ -8,27 +8,10 @@
.set noat
abs.ps $f22,$f8
- absq_s.ph $8,$a0
- absq_s.qb $15,$s1
- absq_s.w $s3,$ra
add.ps $f25,$f27,$f13
- addq.ph $s1,$15,$at
- addq_s.ph $s3,$s6,$s2
- addq_s.w $a2,$8,$at
- addqh.ph $s4,$14,$s1
addqh.w $s7,$s7,$k1
- addqh_r.ph $sp,$25,$s8
addqh_r.w $8,$v1,$zero
- addsc $s8,$15,$12
- addu.ph $a2,$14,$s3
- addu.qb $s6,$v1,$v1
- addu_s.ph $a3,$s3,$gp
- addu_s.qb $s4,$s8,$s1
- adduh.qb $a1,$a1,$at
- adduh_r.qb $a0,$9,$12
- addwc $k0,$s6,$s7
alnv.ps $f12,$f18,$f30,$12
- bitrev $14,$at
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -76,18 +59,6 @@
ceil.l.d $f1,$f3
ceil.l.s $f18,$f13
cfcmsa $s6,$19
- cmp.eq.ph $s7,$14
- cmp.le.ph $8,$14
- cmp.lt.ph $k0,$sp
- cmpgdu.eq.qb $s3,$zero,$k0
- cmpgdu.le.qb $v1,$15,$s2
- cmpgdu.lt.qb $s0,$gp,$sp
- cmpgu.eq.qb $14,$s6,$s8
- cmpgu.le.qb $9,$a3,$s4
- cmpgu.lt.qb $sp,$at,$8
- cmpu.eq.qb $v0,$24
- cmpu.le.qb $s1,$a1
- cmpu.lt.qb $at,$a3
ctcmsa $31,$s7
cvt.d.l $f4,$f16
cvt.ps.s $f3,$f18,$f19
@@ -95,112 +66,44 @@
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmt $k0
- dpa.w.ph $ac1,$s7,$k0
- dpaq_s.w.ph $ac2,$a0,$13
- dpaq_sa.l.w $ac0,$a2,$14
- dpaqx_s.w.ph $ac3,$a0,$24
- dpaqx_sa.w.ph $ac1,$zero,$s5
- dpau.h.qbl $ac1,$10,$24
- dpau.h.qbr $ac1,$s7,$s6
- dpax.w.ph $ac3,$a0,$k0
- dps.w.ph $ac1,$a3,$a1
- dpsq_s.w.ph $ac0,$gp,$k0
- dpsq_sa.l.w $ac0,$a3,$15
- dpsqx_s.w.ph $ac3,$13,$a3
- dpsqx_sa.w.ph $ac3,$sp,$s2
- dpsu.h.qbl $ac2,$14,$10
- dpsu.h.qbr $ac2,$a1,$s6
- dpsx.w.ph $ac0,$s7,$gp
dvpe $s6
emt $8
evpe $v0
- extpdpv $s6,$ac0,$s8
- extpv $13,$ac0,$14
- extrv.w $8,$ac3,$at
- extrv_r.w $8,$ac1,$s6
- extrv_rs.w $gp,$ac1,$s6
- extrv_s.h $s2,$ac1,$14
floor.l.d $f26,$f7
floor.l.s $f12,$f5
fork $s2,$8,$a0
- insv $s2,$at
iret
lbe $14,122($9)
lbue $11,-108($10)
- lbux $9,$14($v0)
lhe $s6,219($v1)
lhue $gp,118($11)
- lhx $sp,$k0($15)
lle $gp,-237($ra)
lwe $ra,-145($14)
lwle $11,-42($11)
lwre $sp,-152($24)
- lwx $12,$12($s4)
madd.ps $f22,$f3,$f14,$f3
- maq_s.w.phl $ac2,$25,$11
- maq_s.w.phr $ac0,$10,$25
- maq_sa.w.phl $ac3,$a1,$v1
- maq_sa.w.phr $ac1,$at,$10
mfgc0 $s6,c0_datahi1
- mflo $9,$ac2
- modsub $a3,$12,$a3
mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
movt.ps $f20,$f25,$fcc2
movz.ps $f18,$f17,$ra
- msub $ac2,$sp,$14
msub.ps $f12,$f14,$f29,$f17
- msubu $ac2,$a1,$24
mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7
- mthi $v0,$ac1
- mthlip $a3,$ac0
- mul.ph $s4,$24,$s0
mul.ps $f14,$f0,$f16
- mul_s.ph $10,$14,$15
- muleq_s.w.phl $11,$s4,$s4
- muleq_s.w.phr $s6,$a0,$s8
- muleu_s.ph.qbl $a2,$14,$8
- muleu_s.ph.qbr $a1,$ra,$9
- mulq_rs.ph $s2,$14,$15
- mulq_rs.w $at,$s4,$25
- mulq_s.ph $s0,$k1,$15
- mulq_s.w $9,$a3,$s0
- mulsa.w.ph $ac1,$s4,$s6
- mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- packrl.ph $ra,$24,$14
- pick.ph $ra,$a2,$gp
- pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15
- precequ.ph.qbl $s7,$ra
- precequ.ph.qbla $a0,$9
- precequ.ph.qbr $ra,$s3
- precequ.ph.qbra $24,$8
- preceu.ph.qbl $sp,$8
- preceu.ph.qbla $s6,$11
- preceu.ph.qbr $gp,$s1
- preceu.ph.qbra $k1,$s0
- precr.qb.ph $v0,$12,$s8
- precrq.ph.w $14,$s8,$24
- precrq.qb.ph $a2,$12,$12
- precrq_rs.ph.w $a1,$k0,$a3
- precrqu_s.qb.ph $zero,$gp,$s5
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
- raddu.w.qb $25,$s3
rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
- repl.ph $at,-307
- replv.ph $v1,$s7
- replv.qb $25,$12
rorv $13,$a3,$s5
round.l.d $f12,$f1
round.l.s $f25,$f5
@@ -209,33 +112,7 @@
sbe $s7,33($s1)
sce $sp,189($10)
she $24,105($v0)
- shilo $ac1,26
- shilov $ac2,$10
- shllv.ph $10,$s0,$s0
- shllv.qb $gp,$v1,$zero
- shllv_s.ph $k1,$at,$13
- shllv_s.w $s1,$ra,$k0
- shrav.ph $25,$s2,$s1
- shrav.qb $zero,$24,$11
- shrav_r.ph $s3,$11,$25
- shrav_r.qb $a0,$sp,$s5
- shrav_r.w $s7,$s4,$s6
- shrlv.ph $14,$10,$9
- shrlv.qb $a2,$s2,$11
sub.ps $f5,$f14,$f26
- subq.ph $ra,$9,$s8
- subq_s.ph $13,$s8,$s5
- subq_s.w $k1,$a2,$a3
- subqh.ph $10,$at,$9
- subqh.w $v0,$a2,$zero
- subqh_r.ph $a0,$12,$s6
- subqh_r.w $10,$a2,$gp
- subu.ph $9,$s6,$s4
- subu.qb $s6,$a2,$s6
- subu_s.ph $v1,$a1,$s3
- subu_s.qb $s1,$at,$ra
- subuh.qb $zero,$gp,$gp
- subuh_r.qb $s4,$s8,$s6
swe $24,94($k0)
swle $v1,-209($gp)
swre $k0,-202($s2)
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s?rev=254911&r1=254910&r2=254911&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid-xfail.s Mon Dec 7 08:12:44 2015
@@ -8,27 +8,10 @@
.set noat
abs.ps $f22,$f8
- absq_s.ph $8,$a0
- absq_s.qb $15,$s1
- absq_s.w $s3,$ra
add.ps $f25,$f27,$f13
- addq.ph $s1,$15,$at
- addq_s.ph $s3,$s6,$s2
- addq_s.w $a2,$8,$at
- addqh.ph $s4,$14,$s1
addqh.w $s7,$s7,$k1
- addqh_r.ph $sp,$25,$s8
addqh_r.w $8,$v1,$zero
- addsc $s8,$15,$12
- addu.ph $a2,$14,$s3
- addu.qb $s6,$v1,$v1
- addu_s.ph $a3,$s3,$gp
- addu_s.qb $s4,$s8,$s1
- adduh.qb $a1,$a1,$at
- adduh_r.qb $a0,$9,$12
- addwc $k0,$s6,$s7
alnv.ps $f12,$f18,$f30,$12
- bitrev $14,$at
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -76,18 +59,6 @@
ceil.l.d $f1,$f3
ceil.l.s $f18,$f13
cfcmsa $s6,$19
- cmp.eq.ph $s7,$14
- cmp.le.ph $8,$14
- cmp.lt.ph $k0,$sp
- cmpgdu.eq.qb $s3,$zero,$k0
- cmpgdu.le.qb $v1,$15,$s2
- cmpgdu.lt.qb $s0,$gp,$sp
- cmpgu.eq.qb $14,$s6,$s8
- cmpgu.le.qb $9,$a3,$s4
- cmpgu.lt.qb $sp,$at,$8
- cmpu.eq.qb $v0,$24
- cmpu.le.qb $s1,$a1
- cmpu.lt.qb $at,$a3
ctcmsa $31,$s7
cvt.d.l $f4,$f16
cvt.ps.s $f3,$f18,$f19
@@ -95,112 +66,44 @@
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmt $k0
- dpa.w.ph $ac1,$s7,$k0
- dpaq_s.w.ph $ac2,$a0,$13
- dpaq_sa.l.w $ac0,$a2,$14
- dpaqx_s.w.ph $ac3,$a0,$24
- dpaqx_sa.w.ph $ac1,$zero,$s5
- dpau.h.qbl $ac1,$10,$24
- dpau.h.qbr $ac1,$s7,$s6
- dpax.w.ph $ac3,$a0,$k0
- dps.w.ph $ac1,$a3,$a1
- dpsq_s.w.ph $ac0,$gp,$k0
- dpsq_sa.l.w $ac0,$a3,$15
- dpsqx_s.w.ph $ac3,$13,$a3
- dpsqx_sa.w.ph $ac3,$sp,$s2
- dpsu.h.qbl $ac2,$14,$10
- dpsu.h.qbr $ac2,$a1,$s6
- dpsx.w.ph $ac0,$s7,$gp
dvpe $s6
emt $8
evpe $v0
- extpdpv $s6,$ac0,$s8
- extpv $13,$ac0,$14
- extrv.w $8,$ac3,$at
- extrv_r.w $8,$ac1,$s6
- extrv_rs.w $gp,$ac1,$s6
- extrv_s.h $s2,$ac1,$14
floor.l.d $f26,$f7
floor.l.s $f12,$f5
fork $s2,$8,$a0
- insv $s2,$at
iret
lbe $14,122($9)
lbue $11,-108($10)
- lbux $9,$14($v0)
lhe $s6,219($v1)
lhue $gp,118($11)
- lhx $sp,$k0($15)
lle $gp,-237($ra)
lwe $ra,-145($14)
lwle $11,-42($11)
lwre $sp,-152($24)
- lwx $12,$12($s4)
madd.ps $f22,$f3,$f14,$f3
- maq_s.w.phl $ac2,$25,$11
- maq_s.w.phr $ac0,$10,$25
- maq_sa.w.phl $ac3,$a1,$v1
- maq_sa.w.phr $ac1,$at,$10
mfgc0 $s6,c0_datahi1
- mflo $9,$ac2
- modsub $a3,$12,$a3
mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
movt.ps $f20,$f25,$fcc2
movz.ps $f18,$f17,$ra
- msub $ac2,$sp,$14
msub.ps $f12,$f14,$f29,$f17
- msubu $ac2,$a1,$24
mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7
- mthi $v0,$ac1
- mthlip $a3,$ac0
- mul.ph $s4,$24,$s0
mul.ps $f14,$f0,$f16
- mul_s.ph $10,$14,$15
- muleq_s.w.phl $11,$s4,$s4
- muleq_s.w.phr $s6,$a0,$s8
- muleu_s.ph.qbl $a2,$14,$8
- muleu_s.ph.qbr $a1,$ra,$9
- mulq_rs.ph $s2,$14,$15
- mulq_rs.w $at,$s4,$25
- mulq_s.ph $s0,$k1,$15
- mulq_s.w $9,$a3,$s0
- mulsa.w.ph $ac1,$s4,$s6
- mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- packrl.ph $ra,$24,$14
- pick.ph $ra,$a2,$gp
- pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15
- precequ.ph.qbl $s7,$ra
- precequ.ph.qbla $a0,$9
- precequ.ph.qbr $ra,$s3
- precequ.ph.qbra $24,$8
- preceu.ph.qbl $sp,$8
- preceu.ph.qbla $s6,$11
- preceu.ph.qbr $gp,$s1
- preceu.ph.qbra $k1,$s0
- precr.qb.ph $v0,$12,$s8
- precrq.ph.w $14,$s8,$24
- precrq.qb.ph $a2,$12,$12
- precrq_rs.ph.w $a1,$k0,$a3
- precrqu_s.qb.ph $zero,$gp,$s5
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
- raddu.w.qb $25,$s3
rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
- repl.ph $at,-307
- replv.ph $v1,$s7
- replv.qb $25,$12
rorv $13,$a3,$s5
round.l.d $f12,$f1
round.l.s $f25,$f5
@@ -209,33 +112,7 @@
sbe $s7,33($s1)
sce $sp,189($10)
she $24,105($v0)
- shilo $ac1,26
- shilov $ac2,$10
- shllv.ph $10,$s0,$s0
- shllv.qb $gp,$v1,$zero
- shllv_s.ph $k1,$at,$13
- shllv_s.w $s1,$ra,$k0
- shrav.ph $25,$s2,$s1
- shrav.qb $zero,$24,$11
- shrav_r.ph $s3,$11,$25
- shrav_r.qb $a0,$sp,$s5
- shrav_r.w $s7,$s4,$s6
- shrlv.ph $14,$10,$9
- shrlv.qb $a2,$s2,$11
sub.ps $f5,$f14,$f26
- subq.ph $ra,$9,$s8
- subq_s.ph $13,$s8,$s5
- subq_s.w $k1,$a2,$a3
- subqh.ph $10,$at,$9
- subqh.w $v0,$a2,$zero
- subqh_r.ph $a0,$12,$s6
- subqh_r.w $10,$a2,$gp
- subu.ph $9,$s6,$s4
- subu.qb $s6,$a2,$s6
- subu_s.ph $v1,$a1,$s3
- subu_s.qb $s1,$at,$ra
- subuh.qb $zero,$gp,$gp
- subuh_r.qb $s4,$s8,$s6
swe $24,94($k0)
swle $v1,-209($gp)
swre $k0,-202($s2)
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s?rev=254911&r1=254910&r2=254911&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s Mon Dec 7 08:12:44 2015
@@ -8,30 +8,10 @@
.set noat
abs.ps $f22,$f8
- absq_s.ph $8,$a0
- absq_s.qb $15,$s1
- absq_s.w $s3,$ra
add.ps $f25,$f27,$f13
- addq.ph $s1,$15,$at
- addq_s.ph $s3,$s6,$s2
- addq_s.w $a2,$8,$at
- addqh.ph $s4,$14,$s1
addqh.w $s7,$s7,$k1
- addqh_r.ph $sp,$25,$s8
addqh_r.w $8,$v1,$zero
- addsc $s8,$15,$12
- addu.ph $a2,$14,$s3
- addu.qb $s6,$v1,$v1
- addu_s.ph $a3,$s3,$gp
- addu_s.qb $s4,$s8,$s1
- adduh.qb $a1,$a1,$at
- adduh_r.qb $a0,$9,$12
- addwc $k0,$s6,$s7
- alnv.ob $v22,$v19,$v30,$v1
- alnv.ob $v31,$v23,$v30,$at
- alnv.ob $v8,$v17,$v30,$a1
alnv.ps $f12,$f18,$f30,$12
- bitrev $14,$at
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -77,18 +57,6 @@
c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
cvt.ps.s $f3,$f18,$f19
- cmp.eq.ph $s7,$14
- cmp.le.ph $8,$14
- cmp.lt.ph $k0,$sp
- cmpgdu.eq.qb $s3,$zero,$k0
- cmpgdu.le.qb $v1,$15,$s2
- cmpgdu.lt.qb $s0,$gp,$sp
- cmpgu.eq.qb $14,$s6,$s8
- cmpgu.le.qb $9,$a3,$s4
- cmpgu.lt.qb $sp,$at,$8
- cmpu.eq.qb $v0,$24
- cmpu.le.qb $s1,$a1
- cmpu.lt.qb $at,$a3
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2
@@ -96,54 +64,22 @@
dmt $k0
dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2
- dpa.w.ph $ac1,$s7,$k0
- dpaq_s.w.ph $ac2,$a0,$13
- dpaq_sa.l.w $ac0,$a2,$14
- dpaqx_s.w.ph $ac3,$a0,$24
- dpaqx_sa.w.ph $ac1,$zero,$s5
- dpau.h.qbl $ac1,$10,$24
- dpau.h.qbr $ac1,$s7,$s6
- dpax.w.ph $ac3,$a0,$k0
- dps.w.ph $ac1,$a3,$a1
- dpsq_s.w.ph $ac0,$gp,$k0
- dpsq_sa.l.w $ac0,$a3,$15
- dpsqx_s.w.ph $ac3,$13,$a3
- dpsqx_sa.w.ph $ac3,$sp,$s2
- dpsu.h.qbl $ac2,$14,$10
- dpsu.h.qbr $ac2,$a1,$s6
- dpsx.w.ph $ac0,$s7,$gp
drorv $at,$a1,$s7
dvpe $s6
emt $8
evpe $v0
- extpdpv $s6,$ac0,$s8
- extpv $13,$ac0,$14
- extrv.w $8,$ac3,$at
- extrv_r.w $8,$ac1,$s6
- extrv_rs.w $gp,$ac1,$s6
- extrv_s.h $s2,$ac1,$14
fork $s2,$8,$a0
- insv $s2,$at
iret
- lbe $14,122($9)
+ lbe $14,122($9)
lbue $11,-108($10)
- lbux $9,$14($v0)
- lhe $s6,219($v1)
+ lhe $s6,219($v1)
lhue $gp,118($11)
- lhx $sp,$k0($15)
- lle $gp,-237($ra)
- lwe $ra,-145($14)
+ lle $gp,-237($ra)
+ lwe $ra,-145($14)
lwle $11,-42($11)
lwre $sp,-152($24)
- lwx $12,$12($s4)
madd.ps $f22,$f3,$f14,$f3
- maq_s.w.phl $ac2,$25,$11
- maq_s.w.phr $ac0,$10,$25
- maq_sa.w.phl $ac3,$a1,$v1
- maq_sa.w.phr $ac1,$at,$10
mfgc0 $s6,c0_datahi1
- mflo $9,$ac2
- modsub $a3,$12,$a3
mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
@@ -151,92 +87,30 @@
movz.ps $f18,$f17,$ra
msgn.qh $v0,$v24,$v20
msgn.qh $v12,$v21,$v0[1]
- msub $ac2,$sp,$14
msub.ps $f12,$f14,$f29,$f17
- msubu $ac2,$a1,$24
mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7
- mthi $v0,$ac1
- mthlip $a3,$ac0
- mul.ph $s4,$24,$s0
mul.ps $f14,$f0,$f16
- mul_s.ph $10,$14,$15
- muleq_s.w.phl $11,$s4,$s4
- muleq_s.w.phr $s6,$a0,$s8
- muleu_s.ph.qbl $a2,$14,$8
- muleu_s.ph.qbr $a1,$ra,$9
- mulq_rs.ph $s2,$14,$15
- mulq_rs.w $at,$s4,$25
- mulq_s.ph $s0,$k1,$15
- mulq_s.w $9,$a3,$s0
- mulsa.w.ph $ac1,$s4,$s6
- mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- packrl.ph $ra,$24,$14
- pick.ph $ra,$a2,$gp
- pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15
- precequ.ph.qbl $s7,$ra
- precequ.ph.qbla $a0,$9
- precequ.ph.qbr $ra,$s3
- precequ.ph.qbra $24,$8
- preceu.ph.qbl $sp,$8
- preceu.ph.qbla $s6,$11
- preceu.ph.qbr $gp,$s1
- preceu.ph.qbra $k1,$s0
- precr.qb.ph $v0,$12,$s8
- precrq.ph.w $14,$s8,$24
- precrq.qb.ph $a2,$12,$12
- precrq_rs.ph.w $a1,$k0,$a3
- precrqu_s.qb.ph $zero,$gp,$s5
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
- raddu.w.qb $25,$s3
rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
- repl.ph $at,-307
- replv.ph $v1,$s7
- replv.qb $25,$12
rorv $13,$a3,$s5
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
- sbe $s7,33($s1)
- sce $sp,189($10)
- she $24,105($v0)
- shilo $ac1,26
- shilov $ac2,$10
- shllv.ph $10,$s0,$s0
- shllv.qb $gp,$v1,$zero
- shllv_s.ph $k1,$at,$13
- shllv_s.w $s1,$ra,$k0
- shrav.ph $25,$s2,$s1
- shrav.qb $zero,$24,$11
- shrav_r.ph $s3,$11,$25
- shrav_r.qb $a0,$sp,$s5
- shrav_r.w $s7,$s4,$s6
- shrlv.ph $14,$10,$9
- shrlv.qb $a2,$s2,$11
+ sbe $s7,33($s1)
+ sce $sp,189($10)
+ she $24,105($v0)
sub.ps $f5,$f14,$f26
- subq.ph $ra,$9,$s8
- subq_s.ph $13,$s8,$s5
- subq_s.w $k1,$a2,$a3
- subqh.ph $10,$at,$9
- subqh.w $v0,$a2,$zero
- subqh_r.ph $a0,$12,$s6
- subqh_r.w $10,$a2,$gp
- subu.ph $9,$s6,$s4
- subu.qb $s6,$a2,$s6
- subu_s.ph $v1,$a1,$s3
- subu_s.qb $s1,$at,$ra
- subuh.qb $zero,$gp,$gp
- subuh_r.qb $s4,$s8,$s6
- swe $24,94($k0)
+ swe $24,94($k0)
swle $v1,-209($gp)
swre $k0,-202($s2)
tlbginv
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s?rev=254911&r1=254910&r2=254911&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid-xfail.s Mon Dec 7 08:12:44 2015
@@ -8,30 +8,13 @@
.set noat
abs.ps $f22,$f8
- absq_s.ph $8,$a0
- absq_s.qb $15,$s1
- absq_s.w $s3,$ra
add.ps $f25,$f27,$f13
- addq.ph $s1,$15,$at
- addq_s.ph $s3,$s6,$s2
- addq_s.w $a2,$8,$at
- addqh.ph $s4,$14,$s1
addqh.w $s7,$s7,$k1
- addqh_r.ph $sp,$25,$s8
addqh_r.w $8,$v1,$zero
- addsc $s8,$15,$12
- addu.ph $a2,$14,$s3
- addu.qb $s6,$v1,$v1
- addu_s.ph $a3,$s3,$gp
- addu_s.qb $s4,$s8,$s1
- adduh.qb $a1,$a1,$at
- adduh_r.qb $a0,$9,$12
- addwc $k0,$s6,$s7
alnv.ob $v22,$v19,$v30,$v1
alnv.ob $v31,$v23,$v30,$at
alnv.ob $v8,$v17,$v30,$a1
alnv.ps $f12,$f18,$f30,$12
- bitrev $14,$at
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -77,18 +60,6 @@
c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
cvt.ps.s $f3,$f18,$f19
- cmp.eq.ph $s7,$14
- cmp.le.ph $8,$14
- cmp.lt.ph $k0,$sp
- cmpgdu.eq.qb $s3,$zero,$k0
- cmpgdu.le.qb $v1,$15,$s2
- cmpgdu.lt.qb $s0,$gp,$sp
- cmpgu.eq.qb $14,$s6,$s8
- cmpgu.le.qb $9,$a3,$s4
- cmpgu.lt.qb $sp,$at,$8
- cmpu.eq.qb $v0,$24
- cmpu.le.qb $s1,$a1
- cmpu.lt.qb $at,$a3
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2
@@ -96,54 +67,22 @@
dmt $k0
dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2
- dpa.w.ph $ac1,$s7,$k0
- dpaq_s.w.ph $ac2,$a0,$13
- dpaq_sa.l.w $ac0,$a2,$14
- dpaqx_s.w.ph $ac3,$a0,$24
- dpaqx_sa.w.ph $ac1,$zero,$s5
- dpau.h.qbl $ac1,$10,$24
- dpau.h.qbr $ac1,$s7,$s6
- dpax.w.ph $ac3,$a0,$k0
- dps.w.ph $ac1,$a3,$a1
- dpsq_s.w.ph $ac0,$gp,$k0
- dpsq_sa.l.w $ac0,$a3,$15
- dpsqx_s.w.ph $ac3,$13,$a3
- dpsqx_sa.w.ph $ac3,$sp,$s2
- dpsu.h.qbl $ac2,$14,$10
- dpsu.h.qbr $ac2,$a1,$s6
- dpsx.w.ph $ac0,$s7,$gp
drorv $at,$a1,$s7
dvpe $s6
emt $8
evpe $v0
- extpdpv $s6,$ac0,$s8
- extpv $13,$ac0,$14
- extrv.w $8,$ac3,$at
- extrv_r.w $8,$ac1,$s6
- extrv_rs.w $gp,$ac1,$s6
- extrv_s.h $s2,$ac1,$14
fork $s2,$8,$a0
- insv $s2,$at
iret
- lbe $14,122($9)
+ lbe $14,122($9)
lbue $11,-108($10)
- lbux $9,$14($v0)
- lhe $s6,219($v1)
+ lhe $s6,219($v1)
lhue $gp,118($11)
- lhx $sp,$k0($15)
- lle $gp,-237($ra)
- lwe $ra,-145($14)
+ lle $gp,-237($ra)
+ lwe $ra,-145($14)
lwle $11,-42($11)
lwre $sp,-152($24)
- lwx $12,$12($s4)
madd.ps $f22,$f3,$f14,$f3
- maq_s.w.phl $ac2,$25,$11
- maq_s.w.phr $ac0,$10,$25
- maq_sa.w.phl $ac3,$a1,$v1
- maq_sa.w.phr $ac1,$at,$10
mfgc0 $s6,c0_datahi1
- mflo $9,$ac2
- modsub $a3,$12,$a3
mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
@@ -151,92 +90,30 @@
movz.ps $f18,$f17,$ra
msgn.qh $v0,$v24,$v20
msgn.qh $v12,$v21,$v0[1]
- msub $ac2,$sp,$14
msub.ps $f12,$f14,$f29,$f17
- msubu $ac2,$a1,$24
mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7
- mthi $v0,$ac1
- mthlip $a3,$ac0
- mul.ph $s4,$24,$s0
mul.ps $f14,$f0,$f16
- mul_s.ph $10,$14,$15
- muleq_s.w.phl $11,$s4,$s4
- muleq_s.w.phr $s6,$a0,$s8
- muleu_s.ph.qbl $a2,$14,$8
- muleu_s.ph.qbr $a1,$ra,$9
- mulq_rs.ph $s2,$14,$15
- mulq_rs.w $at,$s4,$25
- mulq_s.ph $s0,$k1,$15
- mulq_s.w $9,$a3,$s0
- mulsa.w.ph $ac1,$s4,$s6
- mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- packrl.ph $ra,$24,$14
- pick.ph $ra,$a2,$gp
- pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15
- precequ.ph.qbl $s7,$ra
- precequ.ph.qbla $a0,$9
- precequ.ph.qbr $ra,$s3
- precequ.ph.qbra $24,$8
- preceu.ph.qbl $sp,$8
- preceu.ph.qbla $s6,$11
- preceu.ph.qbr $gp,$s1
- preceu.ph.qbra $k1,$s0
- precr.qb.ph $v0,$12,$s8
- precrq.ph.w $14,$s8,$24
- precrq.qb.ph $a2,$12,$12
- precrq_rs.ph.w $a1,$k0,$a3
- precrqu_s.qb.ph $zero,$gp,$s5
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
- raddu.w.qb $25,$s3
rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
- repl.ph $at,-307
- replv.ph $v1,$s7
- replv.qb $25,$12
rorv $13,$a3,$s5
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
- sbe $s7,33($s1)
- sce $sp,189($10)
- she $24,105($v0)
- shilo $ac1,26
- shilov $ac2,$10
- shllv.ph $10,$s0,$s0
- shllv.qb $gp,$v1,$zero
- shllv_s.ph $k1,$at,$13
- shllv_s.w $s1,$ra,$k0
- shrav.ph $25,$s2,$s1
- shrav.qb $zero,$24,$11
- shrav_r.ph $s3,$11,$25
- shrav_r.qb $a0,$sp,$s5
- shrav_r.w $s7,$s4,$s6
- shrlv.ph $14,$10,$9
- shrlv.qb $a2,$s2,$11
+ sbe $s7,33($s1)
+ sce $sp,189($10)
+ she $24,105($v0)
sub.ps $f5,$f14,$f26
- subq.ph $ra,$9,$s8
- subq_s.ph $13,$s8,$s5
- subq_s.w $k1,$a2,$a3
- subqh.ph $10,$at,$9
- subqh.w $v0,$a2,$zero
- subqh_r.ph $a0,$12,$s6
- subqh_r.w $10,$a2,$gp
- subu.ph $9,$s6,$s4
- subu.qb $s6,$a2,$s6
- subu_s.ph $v1,$a1,$s3
- subu_s.qb $s1,$at,$ra
- subuh.qb $zero,$gp,$gp
- subuh_r.qb $s4,$s8,$s6
- swe $24,94($k0)
+ swe $24,94($k0)
swle $v1,-209($gp)
swre $k0,-202($s2)
tlbginv
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s?rev=254911&r1=254910&r2=254911&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid-xfail.s Mon Dec 7 08:12:44 2015
@@ -8,30 +8,13 @@
.set noat
abs.ps $f22,$f8
- absq_s.ph $8,$a0
- absq_s.qb $15,$s1
- absq_s.w $s3,$ra
add.ps $f25,$f27,$f13
- addq.ph $s1,$15,$at
- addq_s.ph $s3,$s6,$s2
- addq_s.w $a2,$8,$at
- addqh.ph $s4,$14,$s1
addqh.w $s7,$s7,$k1
- addqh_r.ph $sp,$25,$s8
addqh_r.w $8,$v1,$zero
- addsc $s8,$15,$12
- addu.ph $a2,$14,$s3
- addu.qb $s6,$v1,$v1
- addu_s.ph $a3,$s3,$gp
- addu_s.qb $s4,$s8,$s1
- adduh.qb $a1,$a1,$at
- adduh_r.qb $a0,$9,$12
- addwc $k0,$s6,$s7
alnv.ob $v22,$v19,$v30,$v1
alnv.ob $v31,$v23,$v30,$at
alnv.ob $v8,$v17,$v30,$a1
alnv.ps $f12,$f18,$f30,$12
- bitrev $14,$at
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
@@ -77,18 +60,6 @@
c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
cvt.ps.s $f3,$f18,$f19
- cmp.eq.ph $s7,$14
- cmp.le.ph $8,$14
- cmp.lt.ph $k0,$sp
- cmpgdu.eq.qb $s3,$zero,$k0
- cmpgdu.le.qb $v1,$15,$s2
- cmpgdu.lt.qb $s0,$gp,$sp
- cmpgu.eq.qb $14,$s6,$s8
- cmpgu.le.qb $9,$a3,$s4
- cmpgu.lt.qb $sp,$at,$8
- cmpu.eq.qb $v0,$24
- cmpu.le.qb $s1,$a1
- cmpu.lt.qb $at,$a3
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2
@@ -96,54 +67,22 @@
dmt $k0
dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2
- dpa.w.ph $ac1,$s7,$k0
- dpaq_s.w.ph $ac2,$a0,$13
- dpaq_sa.l.w $ac0,$a2,$14
- dpaqx_s.w.ph $ac3,$a0,$24
- dpaqx_sa.w.ph $ac1,$zero,$s5
- dpau.h.qbl $ac1,$10,$24
- dpau.h.qbr $ac1,$s7,$s6
- dpax.w.ph $ac3,$a0,$k0
- dps.w.ph $ac1,$a3,$a1
- dpsq_s.w.ph $ac0,$gp,$k0
- dpsq_sa.l.w $ac0,$a3,$15
- dpsqx_s.w.ph $ac3,$13,$a3
- dpsqx_sa.w.ph $ac3,$sp,$s2
- dpsu.h.qbl $ac2,$14,$10
- dpsu.h.qbr $ac2,$a1,$s6
- dpsx.w.ph $ac0,$s7,$gp
drorv $at,$a1,$s7
dvpe $s6
emt $8
evpe $v0
- extpdpv $s6,$ac0,$s8
- extpv $13,$ac0,$14
- extrv.w $8,$ac3,$at
- extrv_r.w $8,$ac1,$s6
- extrv_rs.w $gp,$ac1,$s6
- extrv_s.h $s2,$ac1,$14
fork $s2,$8,$a0
- insv $s2,$at
iret
- lbe $14,122($9)
+ lbe $14,122($9)
lbue $11,-108($10)
- lbux $9,$14($v0)
- lhe $s6,219($v1)
+ lhe $s6,219($v1)
lhue $gp,118($11)
- lhx $sp,$k0($15)
- lle $gp,-237($ra)
- lwe $ra,-145($14)
+ lle $gp,-237($ra)
+ lwe $ra,-145($14)
lwle $11,-42($11)
lwre $sp,-152($24)
- lwx $12,$12($s4)
madd.ps $f22,$f3,$f14,$f3
- maq_s.w.phl $ac2,$25,$11
- maq_s.w.phr $ac0,$10,$25
- maq_sa.w.phl $ac3,$a1,$v1
- maq_sa.w.phr $ac1,$at,$10
mfgc0 $s6,c0_datahi1
- mflo $9,$ac2
- modsub $a3,$12,$a3
mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
@@ -151,92 +90,30 @@
movz.ps $f18,$f17,$ra
msgn.qh $v0,$v24,$v20
msgn.qh $v12,$v21,$v0[1]
- msub $ac2,$sp,$14
msub.ps $f12,$f14,$f29,$f17
- msubu $ac2,$a1,$24
mtc0 $9,c0_datahi1
mtgc0 $s4,$21,7
- mthi $v0,$ac1
- mthlip $a3,$ac0
- mul.ph $s4,$24,$s0
mul.ps $f14,$f0,$f16
- mul_s.ph $10,$14,$15
- muleq_s.w.phl $11,$s4,$s4
- muleq_s.w.phr $s6,$a0,$s8
- muleu_s.ph.qbl $a2,$14,$8
- muleu_s.ph.qbr $a1,$ra,$9
- mulq_rs.ph $s2,$14,$15
- mulq_rs.w $at,$s4,$25
- mulq_s.ph $s0,$k1,$15
- mulq_s.w $9,$a3,$s0
- mulsa.w.ph $ac1,$s4,$s6
- mulsaq_s.w.ph $ac0,$ra,$s2
neg.ps $f19,$f13
nmadd.ps $f27,$f4,$f9,$f25
nmsub.ps $f6,$f12,$f14,$f17
- packrl.ph $ra,$24,$14
- pick.ph $ra,$a2,$gp
- pick.qb $11,$a0,$gp
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
preceq.w.phl $s8,$gp
preceq.w.phr $s5,$15
- precequ.ph.qbl $s7,$ra
- precequ.ph.qbla $a0,$9
- precequ.ph.qbr $ra,$s3
- precequ.ph.qbra $24,$8
- preceu.ph.qbl $sp,$8
- preceu.ph.qbla $s6,$11
- preceu.ph.qbr $gp,$s1
- preceu.ph.qbra $k1,$s0
- precr.qb.ph $v0,$12,$s8
- precrq.ph.w $14,$s8,$24
- precrq.qb.ph $a2,$12,$12
- precrq_rs.ph.w $a1,$k0,$a3
- precrqu_s.qb.ph $zero,$gp,$s5
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
- raddu.w.qb $25,$s3
rdpgpr $s3,$9
recip.d $f19,$f6
recip.s $f3,$f30
- repl.ph $at,-307
- replv.ph $v1,$s7
- replv.qb $25,$12
rorv $13,$a3,$s5
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
- sbe $s7,33($s1)
- sce $sp,189($10)
- she $24,105($v0)
- shilo $ac1,26
- shilov $ac2,$10
- shllv.ph $10,$s0,$s0
- shllv.qb $gp,$v1,$zero
- shllv_s.ph $k1,$at,$13
- shllv_s.w $s1,$ra,$k0
- shrav.ph $25,$s2,$s1
- shrav.qb $zero,$24,$11
- shrav_r.ph $s3,$11,$25
- shrav_r.qb $a0,$sp,$s5
- shrav_r.w $s7,$s4,$s6
- shrlv.ph $14,$10,$9
- shrlv.qb $a2,$s2,$11
+ sbe $s7,33($s1)
+ sce $sp,189($10)
+ she $24,105($v0)
sub.ps $f5,$f14,$f26
- subq.ph $ra,$9,$s8
- subq_s.ph $13,$s8,$s5
- subq_s.w $k1,$a2,$a3
- subqh.ph $10,$at,$9
- subqh.w $v0,$a2,$zero
- subqh_r.ph $a0,$12,$s6
- subqh_r.w $10,$a2,$gp
- subu.ph $9,$s6,$s4
- subu.qb $s6,$a2,$s6
- subu_s.ph $v1,$a1,$s3
- subu_s.qb $s1,$at,$ra
- subuh.qb $zero,$gp,$gp
- subuh_r.qb $s4,$s8,$s6
- swe $24,94($k0)
+ swe $24,94($k0)
swle $v1,-209($gp)
swre $k0,-202($s2)
tlbginv
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