[llvm] r254237 - [X86][AVX] Regenerate ADDSUB tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 28 11:20:49 PST 2015
Author: rksimon
Date: Sat Nov 28 13:20:49 2015
New Revision: 254237
URL: http://llvm.org/viewvc/llvm-project?rev=254237&view=rev
Log:
[X86][AVX] Regenerate ADDSUB tests
Tidied up triple and regenerate tests using update_llc_test_checks.py
Modified:
llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll
llvm/trunk/test/CodeGen/X86/sse3-avx-addsub.ll
Modified: llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll?rev=254237&r1=254236&r2=254237&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3-avx-addsub-2.ll Sat Nov 28 13:20:49 2015
@@ -1,11 +1,20 @@
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
-
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse3 | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefix=AVX
; Verify that we correctly generate 'addsub' instructions from
; a sequence of vector extracts + float add/sub + vector inserts.
define <4 x float> @test1(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test1:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test1:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 0
%2 = extractelement <4 x float> %B, i32 0
%sub = fsub float %1, %2
@@ -24,13 +33,17 @@ define <4 x float> @test1(<4 x float> %A
%vecinsert4 = insertelement <4 x float> %vecinsert3, float %sub2, i32 2
ret <4 x float> %vecinsert4
}
-; CHECK-LABEL: test1
-; SSE: addsubps
-; AVX: vaddsubps
-; CHECK-NEXT: ret
-
define <4 x float> @test2(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test2:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test2:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 2
%2 = extractelement <4 x float> %B, i32 2
%sub2 = fsub float %1, %2
@@ -41,13 +54,17 @@ define <4 x float> @test2(<4 x float> %A
%vecinsert2 = insertelement <4 x float> %vecinsert1, float %add2, i32 3
ret <4 x float> %vecinsert2
}
-; CHECK-LABEL: test2
-; SSE: addsubps
-; AVX: vaddsubps
-; CHECK-NEXT: ret
-
define <4 x float> @test3(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test3:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test3:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 0
%2 = extractelement <4 x float> %B, i32 0
%sub = fsub float %1, %2
@@ -58,13 +75,17 @@ define <4 x float> @test3(<4 x float> %A
%vecinsert2 = insertelement <4 x float> %vecinsert1, float %add, i32 3
ret <4 x float> %vecinsert2
}
-; CHECK-LABEL: test3
-; SSE: addsubps
-; AVX: vaddsubps
-; CHECK-NEXT: ret
-
define <4 x float> @test4(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test4:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test4:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 2
%2 = extractelement <4 x float> %B, i32 2
%sub = fsub float %1, %2
@@ -75,13 +96,17 @@ define <4 x float> @test4(<4 x float> %A
%vecinsert2 = insertelement <4 x float> %vecinsert1, float %add, i32 1
ret <4 x float> %vecinsert2
}
-; CHECK-LABEL: test4
-; SSE: addsubps
-; AVX: vaddsubps
-; CHECK-NEXT: ret
-
define <4 x float> @test5(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test5:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test5:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 0
%2 = extractelement <4 x float> %B, i32 0
%sub2 = fsub float %1, %2
@@ -92,13 +117,17 @@ define <4 x float> @test5(<4 x float> %A
%vecinsert2 = insertelement <4 x float> %vecinsert1, float %add2, i32 1
ret <4 x float> %vecinsert2
}
-; CHECK-LABEL: test5
-; SSE: addsubps
-; AVX: vaddsubps
-; CHECK-NEXT: ret
-
define <4 x float> @test6(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test6:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test6:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 0
%2 = extractelement <4 x float> %B, i32 0
%sub = fsub float %1, %2
@@ -117,13 +146,18 @@ define <4 x float> @test6(<4 x float> %A
%vecinsert4 = insertelement <4 x float> %vecinsert3, float %sub2, i32 2
ret <4 x float> %vecinsert4
}
-; CHECK-LABEL: test6
-; SSE: addsubps
-; AVX: vaddsubps
-; CHECK-NEXT: ret
-
define <4 x double> @test7(<4 x double> %A, <4 x double> %B) {
+; SSE-LABEL: test7:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd %xmm2, %xmm0
+; SSE-NEXT: addsubpd %xmm3, %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test7:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd %ymm1, %ymm0, %ymm0
+; AVX-NEXT: retq
%1 = extractelement <4 x double> %A, i32 0
%2 = extractelement <4 x double> %B, i32 0
%sub = fsub double %1, %2
@@ -142,15 +176,17 @@ define <4 x double> @test7(<4 x double>
%vecinsert4 = insertelement <4 x double> %vecinsert3, double %sub2, i32 2
ret <4 x double> %vecinsert4
}
-; CHECK-LABEL: test7
-; SSE: addsubpd
-; SSE-NEXT: addsubpd
-; AVX: vaddsubpd
-; AVX-NOT: vaddsubpd
-; CHECK: ret
-
define <2 x double> @test8(<2 x double> %A, <2 x double> %B) {
+; SSE-LABEL: test8:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test8:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%1 = extractelement <2 x double> %A, i32 0
%2 = extractelement <2 x double> %B, i32 0
%sub = fsub double %1, %2
@@ -161,13 +197,18 @@ define <2 x double> @test8(<2 x double>
%vecinsert2 = insertelement <2 x double> %vecinsert1, double %add, i32 1
ret <2 x double> %vecinsert2
}
-; CHECK-LABEL: test8
-; SSE: addsubpd
-; AVX: vaddsubpd
-; CHECK: ret
-
define <8 x float> @test9(<8 x float> %A, <8 x float> %B) {
+; SSE-LABEL: test9:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm2, %xmm0
+; SSE-NEXT: addsubps %xmm3, %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test9:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %ymm1, %ymm0, %ymm0
+; AVX-NEXT: retq
%1 = extractelement <8 x float> %A, i32 0
%2 = extractelement <8 x float> %B, i32 0
%sub = fsub float %1, %2
@@ -202,65 +243,118 @@ define <8 x float> @test9(<8 x float> %A
%vecinsert8 = insertelement <8 x float> %vecinsert7, float %sub4, i32 6
ret <8 x float> %vecinsert8
}
-; CHECK-LABEL: test9
-; SSE: addsubps
-; SSE-NEXT: addsubps
-; AVX: vaddsubps
-; AVX-NOT: vaddsubps
-; CHECK: ret
-
; Verify that we don't generate addsub instruction for the following
; functions.
+
define <4 x float> @test10(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test10:
+; SSE: # BB#0:
+; SSE-NEXT: subss %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test10:
+; AVX: # BB#0:
+; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 0
%2 = extractelement <4 x float> %B, i32 0
%sub = fsub float %1, %2
%vecinsert1 = insertelement <4 x float> undef, float %sub, i32 0
ret <4 x float> %vecinsert1
}
-; CHECK-LABEL: test10
-; CHECK-NOT: addsubps
-; CHECK: ret
-
define <4 x float> @test11(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test11:
+; SSE: # BB#0:
+; SSE-NEXT: shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1,0]
+; SSE-NEXT: subss %xmm1, %xmm0
+; SSE-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test11:
+; AVX: # BB#0:
+; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
+; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 2
%2 = extractelement <4 x float> %B, i32 2
%sub = fsub float %1, %2
%vecinsert1 = insertelement <4 x float> undef, float %sub, i32 2
ret <4 x float> %vecinsert1
}
-; CHECK-LABEL: test11
-; CHECK-NOT: addsubps
-; CHECK: ret
-
define <4 x float> @test12(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test12:
+; SSE: # BB#0:
+; SSE-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; SSE-NEXT: movshdup {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; SSE-NEXT: addss %xmm0, %xmm1
+; SSE-NEXT: movsldup {{.*#+}} xmm0 = xmm1[0,0,2,2]
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test12:
+; AVX: # BB#0:
+; AVX-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 1
%2 = extractelement <4 x float> %B, i32 1
%add = fadd float %1, %2
%vecinsert1 = insertelement <4 x float> undef, float %add, i32 1
ret <4 x float> %vecinsert1
}
-; CHECK-LABEL: test12
-; CHECK-NOT: addsubps
-; CHECK: ret
-
define <4 x float> @test13(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test13:
+; SSE: # BB#0:
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1,2,3]
+; SSE-NEXT: addss %xmm0, %xmm1
+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test13:
+; AVX: # BB#0:
+; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]
+; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,1,2,3]
+; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,2,0]
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 3
%2 = extractelement <4 x float> %B, i32 3
%add = fadd float %1, %2
%vecinsert1 = insertelement <4 x float> undef, float %add, i32 3
ret <4 x float> %vecinsert1
}
-; CHECK-LABEL: test13
-; CHECK-NOT: addsubps
-; CHECK: ret
-
define <4 x float> @test14(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test14:
+; SSE: # BB#0:
+; SSE-NEXT: movaps %xmm0, %xmm2
+; SSE-NEXT: subss %xmm1, %xmm2
+; SSE-NEXT: shufpd {{.*#+}} xmm0 = xmm0[1,0]
+; SSE-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1,0]
+; SSE-NEXT: subss %xmm1, %xmm0
+; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1,1,3]
+; SSE-NEXT: movaps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test14:
+; AVX: # BB#0:
+; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm2
+; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
+; AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1],xmm0[0],xmm2[3]
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 0
%2 = extractelement <4 x float> %B, i32 0
%sub = fsub float %1, %2
@@ -271,12 +365,32 @@ define <4 x float> @test14(<4 x float> %
%vecinsert2 = insertelement <4 x float> %vecinsert1, float %sub2, i32 2
ret <4 x float> %vecinsert2
}
-; CHECK-LABEL: test14
-; CHECK-NOT: addsubps
-; CHECK: ret
-
define <4 x float> @test15(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test15:
+; SSE: # BB#0:
+; SSE-NEXT: movshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; SSE-NEXT: movshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
+; SSE-NEXT: addss %xmm3, %xmm2
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1,2,3]
+; SSE-NEXT: addss %xmm0, %xmm1
+; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0,2,1]
+; SSE-NEXT: movaps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test15:
+; AVX: # BB#0:
+; AVX-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
+; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]
+; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,1,2,3]
+; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[0],xmm2[0],xmm0[2,3]
+; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 1
%2 = extractelement <4 x float> %B, i32 1
%add = fadd float %1, %2
@@ -287,12 +401,43 @@ define <4 x float> @test15(<4 x float> %
%vecinsert2 = insertelement <4 x float> %vecinsert1, float %add2, i32 3
ret <4 x float> %vecinsert2
}
-; CHECK-LABEL: test15
-; CHECK-NOT: addsubps
-; CHECK: ret
-
define <4 x float> @test16(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test16:
+; SSE: # BB#0:
+; SSE-NEXT: movaps %xmm0, %xmm2
+; SSE-NEXT: subss %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm0, %xmm3
+; SSE-NEXT: shufpd {{.*#+}} xmm3 = xmm3[1,0]
+; SSE-NEXT: movapd %xmm1, %xmm4
+; SSE-NEXT: shufpd {{.*#+}} xmm4 = xmm4[1,0]
+; SSE-NEXT: subss %xmm4, %xmm3
+; SSE-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; SSE-NEXT: addss %xmm0, %xmm4
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1,2,3]
+; SSE-NEXT: addss %xmm0, %xmm1
+; SSE-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
+; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
+; SSE-NEXT: movaps %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test16:
+; AVX: # BB#0:
+; AVX-NEXT: vsubss %xmm0, %xmm0, %xmm2
+; AVX-NEXT: vpermilpd {{.*#+}} xmm3 = xmm0[1,0]
+; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm1[1,0]
+; AVX-NEXT: vsubss %xmm4, %xmm3, %xmm3
+; AVX-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; AVX-NEXT: vaddss %xmm0, %xmm4, %xmm4
+; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]
+; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,1,2,3]
+; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm4[0],xmm2[2,3]
+; AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
+; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
+; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 0
%2 = extractelement <4 x float> %B, i32 0
%sub = fsub float %1, undef
@@ -311,11 +456,17 @@ define <4 x float> @test16(<4 x float> %
%vecinsert4 = insertelement <4 x float> %vecinsert3, float %sub2, i32 2
ret <4 x float> %vecinsert4
}
-; CHECK-LABEL: test16
-; CHECK-NOT: addsubps
-; CHECK: ret
define <2 x float> @test_v2f32(<2 x float> %v0, <2 x float> %v1) {
+; SSE-LABEL: test_v2f32:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v2f32:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%v2 = extractelement <2 x float> %v0, i32 0
%v3 = extractelement <2 x float> %v1, i32 0
%v4 = extractelement <2 x float> %v0, i32 1
@@ -326,6 +477,3 @@ define <2 x float> @test_v2f32(<2 x floa
%res1 = insertelement <2 x float> %res0, float %add, i32 1
ret <2 x float> %res1
}
-; CHECK-LABEL: test_v2f32
-; CHECK: addsubps %xmm1, %xmm0
-; CHECK-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/sse3-avx-addsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3-avx-addsub.ll?rev=254237&r1=254236&r2=254237&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3-avx-addsub.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3-avx-addsub.ll Sat Nov 28 13:20:49 2015
@@ -1,5 +1,6 @@
-; RUN: llc < %s -march=x86-64 -mcpu=core2 | FileCheck %s -check-prefix=SSE -check-prefix=CHECK
-; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX -check-prefix=CHECK
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse3 | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefix=AVX
; Test ADDSUB ISel patterns.
@@ -35,109 +36,137 @@
; }
define <4 x float> @test1(<4 x float> %A, <4 x float> %B) {
+; SSE-LABEL: test1:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test1:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%sub = fsub <4 x float> %A, %B
%add = fadd <4 x float> %A, %B
%vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
ret <4 x float> %vecinit6
}
-; CHECK-LABEL: test1
-; SSE: addsubps
-; AVX: vaddsubps
-; CHECK-NEXT: ret
-
define <8 x float> @test2(<8 x float> %A, <8 x float> %B) {
+; SSE-LABEL: test2:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps %xmm2, %xmm0
+; SSE-NEXT: addsubps %xmm3, %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test2:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps %ymm1, %ymm0, %ymm0
+; AVX-NEXT: retq
%sub = fsub <8 x float> %A, %B
%add = fadd <8 x float> %A, %B
%vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
ret <8 x float> %vecinit14
}
-; CHECK-LABEL: test2
-; SSE: addsubps
-; SSE-NEXT: addsubps
-; AVX: vaddsubps
-; AVX-NOT: vaddsubps
-; CHECK: ret
-
define <4 x double> @test3(<4 x double> %A, <4 x double> %B) {
+; SSE-LABEL: test3:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd %xmm2, %xmm0
+; SSE-NEXT: addsubpd %xmm3, %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test3:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd %ymm1, %ymm0, %ymm0
+; AVX-NEXT: retq
%sub = fsub <4 x double> %A, %B
%add = fadd <4 x double> %A, %B
%vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
ret <4 x double> %vecinit6
}
-; CHECK-LABEL: test3
-; SSE: addsubpd
-; SSE: addsubpd
-; AVX: vaddsubpd
-; AVX-NOT: vaddsubpd
-; CHECK: ret
-
define <2 x double> @test4(<2 x double> %A, <2 x double> %B) #0 {
+; SSE-LABEL: test4:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test4:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
%add = fadd <2 x double> %A, %B
%sub = fsub <2 x double> %A, %B
%vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
ret <2 x double> %vecinit2
}
-; CHECK-LABEL: test4
-; SSE: addsubpd
-; AVX: vaddsubpd
-; CHECK-NEXT: ret
-
define <4 x float> @test1b(<4 x float> %A, <4 x float>* %B) {
+; SSE-LABEL: test1b:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test1b:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps (%rdi), %xmm0, %xmm0
+; AVX-NEXT: retq
%1 = load <4 x float>, <4 x float>* %B
%add = fadd <4 x float> %A, %1
%sub = fsub <4 x float> %A, %1
%vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
ret <4 x float> %vecinit6
}
-; CHECK-LABEL: test1b
-; SSE: addsubps
-; AVX: vaddsubps
-; CHECK-NEXT: ret
-
define <8 x float> @test2b(<8 x float> %A, <8 x float>* %B) {
+; SSE-LABEL: test2b:
+; SSE: # BB#0:
+; SSE-NEXT: addsubps (%rdi), %xmm0
+; SSE-NEXT: addsubps 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test2b:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubps (%rdi), %ymm0, %ymm0
+; AVX-NEXT: retq
%1 = load <8 x float>, <8 x float>* %B
%add = fadd <8 x float> %A, %1
%sub = fsub <8 x float> %A, %1
%vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
ret <8 x float> %vecinit14
}
-; CHECK-LABEL: test2b
-; SSE: addsubps
-; SSE-NEXT: addsubps
-; AVX: vaddsubps
-; AVX-NOT: vaddsubps
-; CHECK: ret
-
define <4 x double> @test3b(<4 x double> %A, <4 x double>* %B) {
+; SSE-LABEL: test3b:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd (%rdi), %xmm0
+; SSE-NEXT: addsubpd 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test3b:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd (%rdi), %ymm0, %ymm0
+; AVX-NEXT: retq
%1 = load <4 x double>, <4 x double>* %B
%add = fadd <4 x double> %A, %1
%sub = fsub <4 x double> %A, %1
%vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
ret <4 x double> %vecinit6
}
-; CHECK-LABEL: test3b
-; SSE: addsubpd
-; SSE: addsubpd
-; AVX: vaddsubpd
-; AVX-NOT: vaddsubpd
-; CHECK: ret
-
define <2 x double> @test4b(<2 x double> %A, <2 x double>* %B) {
+; SSE-LABEL: test4b:
+; SSE: # BB#0:
+; SSE-NEXT: addsubpd (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test4b:
+; AVX: # BB#0:
+; AVX-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0
+; AVX-NEXT: retq
%1 = load <2 x double>, <2 x double>* %B
%sub = fsub <2 x double> %A, %1
%add = fadd <2 x double> %A, %1
%vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
ret <2 x double> %vecinit2
}
-; CHECK-LABEL: test4b
-; SSE: addsubpd
-; AVX: vaddsubpd
-; CHECK-NEXT: ret
-
More information about the llvm-commits
mailing list