[PATCH] D15018: [AArch64] Add ARMv8.2-A new AT instruction variants

[Oliver Stannard via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL254159: [AArch64] Add ARMv8.2-A new AT instruction variants (authored by olista01).

Changed prior to commit:
  http://reviews.llvm.org/D15018?vs=41239&id=41256#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D15018

Files:
  llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
  llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
  llvm/trunk/test/MC/AArch64/armv8.2a-at.s
  llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-at.txt

Index: llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-at.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-at.txt
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-at.txt
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.2a --disassemble < %s | FileCheck %s --check-prefix=NO_V82
+
+[0x01,0x79,0x08,0xd5]
+[0x22,0x79,0x08,0xd5]
+# CHECK: at s1e1rp, x1
+# CHECK: at s1e1wp, x2
+# NO_V82: sys     #0, c7, c9, #0, x1
+# NO_V82: sys     #0, c7, c9, #1, x2
Index: llvm/trunk/test/MC/AArch64/armv8.2a-at.s
===================================================================
--- llvm/trunk/test/MC/AArch64/armv8.2a-at.s
+++ llvm/trunk/test/MC/AArch64/armv8.2a-at.s
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+  at s1e1rp, x1
+  at s1e1wp, x2
+// CHECK: at      s1e1rp, x1              // encoding: [0x01,0x79,0x08,0xd5]
+// CHECK: at      s1e1wp, x2              // encoding: [0x22,0x79,0x08,0xd5]
+// ERROR: error: AT S1E1RP requires ARMv8.2a
+// ERROR: error: AT S1E1WP requires ARMv8.2a
Index: llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
===================================================================
--- llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -337,7 +337,9 @@
     S12E1R = 0x63c4, // 01  100  0111  1000  100
     S12E1W = 0x63c5, // 01  100  0111  1000  101
     S12E0R = 0x63c6, // 01  100  0111  1000  110
-    S12E0W = 0x63c7  // 01  100  0111  1000  111
+    S12E0W = 0x63c7, // 01  100  0111  1000  111
+    S1E1RP = 0x43c8, // 01  000  0111  1001  000
+    S1E1WP = 0x43c9  // 01  000  0111  1001  001
   };
 
   struct ATMapper : AArch64NamedImmMapper {
Index: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2513,6 +2513,20 @@
     } else if (!Op.compare_lower("s12e0w")) {
       // SYS #4, C7, C8, #7
       SYS_ALIAS(4, 7, 8, 7);
+    } else if (!Op.compare_lower("s1e1rp")) {
+      if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
+        // SYS #0, C7, C9, #0
+        SYS_ALIAS(0, 7, 9, 0);
+      } else {
+        return TokError("AT S1E1RP requires ARMv8.2a");
+      }
+    } else if (!Op.compare_lower("s1e1wp")) {
+      if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
+        // SYS #0, C7, C9, #1
+        SYS_ALIAS(0, 7, 9, 1);
+      } else {
+        return TokError("AT S1E1WP requires ARMv8.2a");
+      }
     } else {
       return TokError("invalid operand for AT instruction");
     }
Index: llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
+++ llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
@@ -780,6 +780,21 @@
         break;
       }
       break;
+    case 9:
+      switch (Op1Val) {
+      default:
+        break;
+      case 0:
+        if (STI.getFeatureBits()[AArch64::HasV8_2aOps]) {
+          switch (Op2Val) {
+          default:
+            break;
+          case 0: Asm = "at\ts1e1rp"; break;
+          case 1: Asm = "at\ts1e1wp"; break;
+          }
+        }
+        break;
+      }
     }
   } else if (CnVal == 8) {
     // TLBI aliases


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