[llvm] r254148 - [mips][ias] Explicitly disable IAS on tests that depend on not assembling.
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 26 03:23:03 PST 2015
Author: dsanders
Date: Thu Nov 26 05:23:03 2015
New Revision: 254148
URL: http://llvm.org/viewvc/llvm-project?rev=254148&view=rev
Log:
[mips][ias] Explicitly disable IAS on tests that depend on not assembling.
Summary:
no-odd-spreg-msa.ll: This test deliberately uses an odd-numbered register
in inline assembly and expects the compiler to insert a move to an
even-numbered register.
inlineasm-operand-code.ll and inlineasm_constraint.ll:
Checks for IAS's output will be added once a matcher bug is resolved. This bug
causes the canonical output emitted by IAS to be incorrect for uimm16 constants
with the MSB set. We will still need the non-IAS checks at this point since
these tests primarily test formatting of operands.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D14705
Modified:
llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll
llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll
llvm/trunk/test/CodeGen/Mips/no-odd-spreg-msa.ll
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll?rev=254148&r1=254147&r2=254148&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-operand-code.ll Thu Nov 26 05:23:03 2015
@@ -1,7 +1,9 @@
; Positive test for inline register constraints
;
-; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=CHECK_LITTLE_32 %s
-; RUN: llc -march=mips < %s | FileCheck -check-prefix=CHECK_BIG_32 %s
+; RUN: llc -no-integrated-as -march=mipsel < %s | \
+; RUN: FileCheck -check-prefix=ALL -check-prefix=LE32 -check-prefix=GAS %s
+; RUN: llc -no-integrated-as -march=mips < %s | \
+; RUN: FileCheck -check-prefix=ALL -check-prefix=BE32 -check-prefix=GAS %s
%union.u_tag = type { i64 }
%struct.anon = type { i32, i32 }
@@ -10,10 +12,10 @@
; X with -3
define i32 @constraint_X() nounwind {
entry:
-;CHECK_LITTLE_32-LABEL: constraint_X:
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd
-;CHECK_LITTLE_32: #NO_APP
+; ALL-LABEL: constraint_X:
+; ALL: #APP
+; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd
+; ALL: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, ${2:X}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@@ -21,10 +23,10 @@ entry:
; x with -3
define i32 @constraint_x() nounwind {
entry:
-;CHECK_LITTLE_32-LABEL: constraint_x:
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd
-;CHECK_LITTLE_32: #NO_APP
+; ALL-LABEL: constraint_x:
+; ALL: #APP
+; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd
+; ALL: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, ${2:x}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@@ -32,10 +34,10 @@ entry:
; d with -3
define i32 @constraint_d() nounwind {
entry:
-;CHECK_LITTLE_32-LABEL: constraint_d:
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
-;CHECK_LITTLE_32: #NO_APP
+; ALL-LABEL: constraint_d:
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
+; ALL: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, ${2:d}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@@ -43,10 +45,10 @@ entry:
; m with -3
define i32 @constraint_m() nounwind {
entry:
-;CHECK_LITTLE_32-LABEL: constraint_m:
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, -4
-;CHECK_LITTLE_32: #NO_APP
+; ALL-LABEL: constraint_m:
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -4
+; ALL: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, ${2:m}", "=r,r,I"(i32 7, i32 -3) ;
ret i32 0
}
@@ -54,125 +56,106 @@ entry:
; z with -3
define i32 @constraint_z() nounwind {
entry:
-;CHECK_LITTLE_32-LABEL: constraint_z:
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
-;CHECK_LITTLE_32: #NO_APP
+; ALL-LABEL: constraint_z:
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
+; ALL: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 -3) ;
; z with 0
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, $0
-;CHECK_LITTLE_32: #NO_APP
+; ALL: #APP
+; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, $0
+; ALL: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
; z with non-zero and the "r"(register) and "J"(integer zero) constraints
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
-;CHECK_LITTLE_32: #NO_APP
+; ALL: #APP
+; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
+; ALL: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
; z with zero and the "r"(register) and "J"(integer zero) constraints
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: mtc0 $0, ${{[0-9]+}}
-;CHECK_LITTLE_32: #NO_APP
+; ALL: #APP
+; ALL: mtc0 $0, ${{[0-9]+}}
+; ALL: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
; z with non-zero and just the "r"(register) constraint
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
-;CHECK_LITTLE_32: #NO_APP
+; ALL: #APP
+; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
+; ALL: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
; z with zero and just the "r"(register) constraint
; FIXME: Check for $0, instead of other registers.
; We should be using $0 directly in this case, not real registers.
; When the materialization of 0 gets fixed, this test will fail.
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
-;CHECK_LITTLE_32: #NO_APP
+; ALL: #APP
+; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
+; ALL: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
ret i32 0
}
-; a long long in 32 bit mode (use to assert)
+; A long long in 32 bit mode (use to assert)
define i32 @constraint_longlong() nounwind {
entry:
-;CHECK_LITTLE_32-LABEL: constraint_longlong:
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
-;CHECK_LITTLE_32: #NO_APP
+; ALL-LABEL: constraint_longlong:
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
+; ALL: #NO_APP
tail call i64 asm sideeffect "addiu $0, $1, $2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
ret i32 0
}
-; D, in little endian the source reg will be 4 bytes into the long long
+; In little endian the source reg will be 4 bytes into the long long
+; In big endian the source reg will also be 4 bytes into the long long
define i32 @constraint_D() nounwind {
entry:
-;CHECK_LITTLE_32-LABEL: constraint_D:
-;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
-;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
-;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
-;CHECK_LITTLE_32: #NO_APP
-
-; D, in big endian the source reg will also be 4 bytes into the long long
-;CHECK_BIG_32-LABEL: constraint_D:
-;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
-;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
-;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
-;CHECK_BIG_32: #APP
-;CHECK_BIG_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
-;CHECK_BIG_32: #NO_APP
+; ALL-LABEL: constraint_D:
+; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
+; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
+; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
+; ALL: #APP
+; LE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
+; BE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
+; ALL: #NO_APP
%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
%trunc1 = trunc i64 %bosco to i32
tail call i32 asm sideeffect "or $0, ${1:D}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
ret i32 0
}
-; L, in little endian the source reg will be 0 bytes into the long long
+; In little endian the source reg will be 0 bytes into the long long
+; In big endian the source reg will be 4 bytes into the long long
define i32 @constraint_L() nounwind {
entry:
-;CHECK_LITTLE_32-LABEL: constraint_L:
-;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
-;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
-;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
-;CHECK_LITTLE_32: #NO_APP
-; L, in big endian the source reg will be 4 bytes into the long long
-;CHECK_BIG_32-LABEL: constraint_L:
-;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
-;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
-;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
-;CHECK_BIG_32: #APP
-;CHECK_BIG_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
-;CHECK_BIG_32: #NO_APP
+; ALL-LABEL: constraint_L:
+; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
+; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
+; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
+; ALL: #APP
+; LE32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
+; BE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
+; ALL: #NO_APP
%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
%trunc1 = trunc i64 %bosco to i32
tail call i32 asm sideeffect "or $0, ${1:L}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
ret i32 0
}
-; M, in little endian the source reg will be 4 bytes into the long long
+; In little endian the source reg will be 4 bytes into the long long
+; In big endian the source reg will be 0 bytes into the long long
define i32 @constraint_M() nounwind {
entry:
-;CHECK_LITTLE_32-LABEL: constraint_M:
-;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
-;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
-;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
-;CHECK_LITTLE_32: #APP
-;CHECK_LITTLE_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
-;CHECK_LITTLE_32: #NO_APP
-; M, in big endian the source reg will be 0 bytes into the long long
-;CHECK_BIG_32-LABEL: constraint_M:
-;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
-;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
-;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
-;CHECK_BIG_32: #APP
-;CHECK_BIG_32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
-;CHECK_BIG_32: #NO_APP
+; ALL-LABEL: constraint_M:
+; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
+; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
+; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
+; ALL: #APP
+; LE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
+; BE32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
+; ALL: #NO_APP
%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
%trunc1 = trunc i64 %bosco to i32
tail call i32 asm sideeffect "or $0, ${1:M}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
Modified: llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll?rev=254148&r1=254147&r2=254148&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll Thu Nov 26 05:23:03 2015
@@ -1,55 +1,73 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
-
-define i32 @main() nounwind {
-entry:
+; RUN: llc -no-integrated-as -march=mipsel < %s | \
+; RUN: FileCheck %s -check-prefix=ALL -check-prefix=GAS
+define void @constraint_I() nounwind {
; First I with short
-; CHECK: #APP
-; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 4096
-; CHECK: #NO_APP
+; ALL-LABEL: constraint_I:
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 4096
+; ALL: #NO_APP
tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i16 7, i16 4096) nounwind
; Then I with int
-; CHECK: #APP
-; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
-; CHECK: #NO_APP
- tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i32 7, i32 -3) nounwind
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
+; ALL: #NO_APP
+ tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i32 7, i32 -3) nounwind
+ ret void
+}
+define void @constraint_J() nounwind {
; Now J with 0
-; CHECK: #APP
-; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0
-; CHECK: #NO_APP
+; ALL-LABEL: constraint_J:
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0
+; ALL: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, $2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
+ ret void
+}
+define void @constraint_K() nounwind {
; Now K with 64
-; CHECK: #APP
-; CHECK: addu ${{[0-9]+}}, ${{[0-9]+}}, 64
-; CHECK: #NO_APP
+; ALL: #APP
+; GAS: addu ${{[0-9]+}}, ${{[0-9]+}}, 64
+; ALL: #NO_APP
tail call i16 asm sideeffect "addu $0, $1, $2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind
+ ret void
+}
+define void @constraint_L() nounwind {
; Now L with 0x00100000
-; CHECK: #APP
-; CHECK: add ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
-; CHECK: #NO_APP
+; ALL: #APP
+; ALL: add ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; ALL: #NO_APP
tail call i32 asm sideeffect "add $0, $1, $3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind
+ ret void
+}
+define void @constraint_N() nounwind {
; Now N with -3
-; CHECK: #APP
-; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
-; CHECK: #NO_APP
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
+; ALL: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,N"(i32 7, i32 -3) nounwind
+ ret void
+}
+define void @constraint_O() nounwind {
; Now O with -3
-; CHECK: #APP
-; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
-; CHECK: #NO_APP
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
+; ALL: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,O"(i32 7, i16 -3) nounwind
+ ret void
+}
+define void @constraint_P() nounwind {
; Now P with 65535
-; CHECK: #APP
-; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 65535
-; CHECK: #NO_APP
+; ALL: #APP
+; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 65535
+; ALL: #NO_APP
tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,P"(i32 7, i32 65535) nounwind
-
- ret i32 0
+ ret void
}
Modified: llvm/trunk/test/CodeGen/Mips/no-odd-spreg-msa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/no-odd-spreg-msa.ll?rev=254148&r1=254147&r2=254148&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/no-odd-spreg-msa.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/no-odd-spreg-msa.ll Thu Nov 26 05:23:03 2015
@@ -1,5 +1,9 @@
-; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,-nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=ODDSPREG
-; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOODDSPREG
+; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,-nooddspreg \
+; RUN: -no-integrated-as < %s | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=ODDSPREG
+; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,+nooddspreg \
+; RUN: -no-integrated-as < %s | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=NOODDSPREG
@v4f32 = global <4 x float> zeroinitializer
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