[llvm] r254095 - AMDGPU/SI: select S_ABS_I32 when possible (v2)
Marek Olsak via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 25 13:22:45 PST 2015
Author: mareko
Date: Wed Nov 25 15:22:45 2015
New Revision: 254095
URL: http://llvm.org/viewvc/llvm-project?rev=254095&view=rev
Log:
AMDGPU/SI: select S_ABS_I32 when possible (v2)
v2: added more tests, moved the SALU->VALU conversion to a separate function
It looks like it's not possible to get subregisters in the S_ABS lowering
code, and I don't feel like guessing without testing what the correct code
would look like.
Added:
llvm/trunk/test/CodeGen/AMDGPU/sminmax.ll
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=254095&r1=254094&r2=254095&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Wed Nov 25 15:22:45 2015
@@ -2412,6 +2412,11 @@ void SIInstrInfo::moveToVALU(MachineInst
}
break;
+ case AMDGPU::S_ABS_I32:
+ lowerScalarAbs(Worklist, Inst);
+ Inst->eraseFromParent();
+ continue;
+
case AMDGPU::S_BFE_U64:
case AMDGPU::S_BFM_B64:
llvm_unreachable("Moving this op to VALU not implemented");
@@ -2497,6 +2502,30 @@ const TargetRegisterClass *SIInstrInfo::
return &AMDGPU::VGPR_32RegClass;
}
+void SIInstrInfo::lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
+ MachineInstr *Inst) const {
+ MachineBasicBlock &MBB = *Inst->getParent();
+ MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
+ MachineBasicBlock::iterator MII = Inst;
+ DebugLoc DL = Inst->getDebugLoc();
+
+ MachineOperand &Dest = Inst->getOperand(0);
+ MachineOperand &Src = Inst->getOperand(1);
+ unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+
+ BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg)
+ .addImm(0)
+ .addReg(Src.getReg());
+
+ BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
+ .addReg(Src.getReg())
+ .addReg(TmpReg);
+
+ MRI.replaceRegWith(Dest.getReg(), ResultReg);
+ addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
+}
+
void SIInstrInfo::splitScalar64BitUnaryOp(
SmallVectorImpl<MachineInstr *> &Worklist,
MachineInstr *Inst,
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h?rev=254095&r1=254094&r2=254095&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h Wed Nov 25 15:22:45 2015
@@ -41,6 +41,9 @@ private:
void swapOperands(MachineBasicBlock::iterator Inst) const;
+ void lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
+ MachineInstr *Inst) const;
+
void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
MachineInstr *Inst, unsigned Opcode) const;
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=254095&r1=254094&r2=254095&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Wed Nov 25 15:22:45 2015
@@ -2174,6 +2174,11 @@ def : Pat <
(S_MOV_B32 0), sub1))
>;
+def : Pat <
+ (i32 (smax i32:$x, (i32 (ineg i32:$x)))),
+ (S_ABS_I32 $x)
+>;
+
//===----------------------------------------------------------------------===//
// SOP2 Patterns
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll?rev=254095&r1=254094&r2=254095&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll Wed Nov 25 15:22:45 2015
@@ -8,9 +8,7 @@ declare i32 @llvm.AMDGPU.abs(i32) nounwi
declare i32 @llvm.AMDIL.abs.i32(i32) nounwind readnone
; FUNC-LABEL: {{^}}s_abs_i32:
-; SI: s_sub_i32
-; SI: s_max_i32
-; SI: s_endpgm
+; SI: s_abs_i32
; EG: SUB_INT
; EG: MAX_INT
Added: llvm/trunk/test/CodeGen/AMDGPU/sminmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sminmax.ll?rev=254095&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/sminmax.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/sminmax.ll Wed Nov 25 15:22:45 2015
@@ -0,0 +1,156 @@
+; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
+
+; FUNC-LABEL: {{^}}s_abs_i32:
+; GCN: s_abs_i32
+; GCN: s_add_i32
+define void @s_abs_i32(i32 addrspace(1)* %out, i32 %val) nounwind {
+ %neg = sub i32 0, %val
+ %cond = icmp sgt i32 %val, %neg
+ %res = select i1 %cond, i32 %val, i32 %neg
+ %res2 = add i32 %res, 2
+ store i32 %res2, i32 addrspace(1)* %out, align 4
+ ret void
+}
+
+; FUNC-LABEL: {{^}}v_abs_i32:
+; GCN: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SRC:v[0-9]+]]
+; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG]], [[SRC]]
+; GCN: v_add_i32
+define void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind {
+ %val = load i32, i32 addrspace(1)* %src, align 4
+ %neg = sub i32 0, %val
+ %cond = icmp sgt i32 %val, %neg
+ %res = select i1 %cond, i32 %val, i32 %neg
+ %res2 = add i32 %res, 2
+ store i32 %res2, i32 addrspace(1)* %out, align 4
+ ret void
+}
+
+; FUNC-LABEL: {{^}}s_abs_v2i32:
+; TODO: this should use s_abs_i32
+; GCNX: s_abs_i32
+; GCNX: s_abs_i32
+; GCN: s_sub
+; GCN: s_sub
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cndmask_b32
+; GCN-DAG: v_cndmask_b32
+; GCN: v_add_i32
+; GCN: v_add_i32
+define void @s_abs_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %val) nounwind {
+ %z0 = insertelement <2 x i32> undef, i32 0, i32 0
+ %z1 = insertelement <2 x i32> %z0, i32 0, i32 1
+ %t0 = insertelement <2 x i32> undef, i32 2, i32 0
+ %t1 = insertelement <2 x i32> %t0, i32 2, i32 1
+ %neg = sub <2 x i32> %z1, %val
+ %cond = icmp sgt <2 x i32> %val, %neg
+ %res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg
+ %res2 = add <2 x i32> %res, %t1
+ store <2 x i32> %res2, <2 x i32> addrspace(1)* %out, align 4
+ ret void
+}
+
+; FUNC-LABEL: {{^}}v_abs_v2i32:
+; GCN: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
+; GCN: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
+; TODO: this should use v_max_i32
+; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]]
+; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]]
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cndmask_b32
+; GCN-DAG: v_cndmask_b32
+; GCN: v_add_i32
+; GCN: v_add_i32
+define void @v_abs_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %src) nounwind {
+ %z0 = insertelement <2 x i32> undef, i32 0, i32 0
+ %z1 = insertelement <2 x i32> %z0, i32 0, i32 1
+ %t0 = insertelement <2 x i32> undef, i32 2, i32 0
+ %t1 = insertelement <2 x i32> %t0, i32 2, i32 1
+ %val = load <2 x i32>, <2 x i32> addrspace(1)* %src, align 4
+ %neg = sub <2 x i32> %z1, %val
+ %cond = icmp sgt <2 x i32> %val, %neg
+ %res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg
+ %res2 = add <2 x i32> %res, %t1
+ store <2 x i32> %res2, <2 x i32> addrspace(1)* %out, align 4
+ ret void
+}
+
+; FUNC-LABEL: {{^}}s_abs_v4i32:
+; TODO: this should use s_abs_i32
+; GCNX: s_abs_i32
+; GCNX: s_abs_i32
+; GCNX: s_abs_i32
+; GCNX: s_abs_i32
+; GCN: s_sub
+; GCN: s_sub
+; GCN: s_sub
+; GCN: s_sub
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cndmask_b32
+; GCN-DAG: v_cndmask_b32
+; GCN-DAG: v_cndmask_b32
+; GCN-DAG: v_cndmask_b32
+; GCN: v_add_i32
+; GCN: v_add_i32
+define void @s_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %val) nounwind {
+ %z0 = insertelement <4 x i32> undef, i32 0, i32 0
+ %z1 = insertelement <4 x i32> %z0, i32 0, i32 1
+ %z2 = insertelement <4 x i32> %z1, i32 0, i32 2
+ %z3 = insertelement <4 x i32> %z2, i32 0, i32 3
+ %t0 = insertelement <4 x i32> undef, i32 2, i32 0
+ %t1 = insertelement <4 x i32> %t0, i32 2, i32 1
+ %t2 = insertelement <4 x i32> %t1, i32 2, i32 2
+ %t3 = insertelement <4 x i32> %t2, i32 2, i32 3
+ %neg = sub <4 x i32> %z3, %val
+ %cond = icmp sgt <4 x i32> %val, %neg
+ %res = select <4 x i1> %cond, <4 x i32> %val, <4 x i32> %neg
+ %res2 = add <4 x i32> %res, %t3
+ store <4 x i32> %res2, <4 x i32> addrspace(1)* %out, align 4
+ ret void
+}
+
+; FUNC-LABEL: {{^}}v_abs_v4i32:
+; GCN: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
+; GCN: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
+; GCN: v_sub_i32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]]
+; GCN: v_sub_i32_e32 [[NEG3:v[0-9]+]], vcc, 0, [[SRC3:v[0-9]+]]
+; TODO: this should use v_max_i32
+; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]]
+; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]]
+; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG2]], [[SRC2]]
+; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG3]], [[SRC3]]
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cmp_gt
+; GCN-DAG: v_cndmask_b32
+; GCN-DAG: v_cndmask_b32
+; GCN-DAG: v_cndmask_b32
+; GCN-DAG: v_cndmask_b32
+; GCN: v_add_i32
+; GCN: v_add_i32
+; GCN: v_add_i32
+; GCN: v_add_i32
+define void @v_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %src) nounwind {
+ %z0 = insertelement <4 x i32> undef, i32 0, i32 0
+ %z1 = insertelement <4 x i32> %z0, i32 0, i32 1
+ %z2 = insertelement <4 x i32> %z1, i32 0, i32 2
+ %z3 = insertelement <4 x i32> %z2, i32 0, i32 3
+ %t0 = insertelement <4 x i32> undef, i32 2, i32 0
+ %t1 = insertelement <4 x i32> %t0, i32 2, i32 1
+ %t2 = insertelement <4 x i32> %t1, i32 2, i32 2
+ %t3 = insertelement <4 x i32> %t2, i32 2, i32 3
+ %val = load <4 x i32>, <4 x i32> addrspace(1)* %src, align 4
+ %neg = sub <4 x i32> %z3, %val
+ %cond = icmp sgt <4 x i32> %val, %neg
+ %res = select <4 x i1> %cond, <4 x i32> %val, <4 x i32> %neg
+ %res2 = add <4 x i32> %res, %t3
+ store <4 x i32> %res2, <4 x i32> addrspace(1)* %out, align 4
+ ret void
+}
More information about the llvm-commits
mailing list