[PATCH] D14994: Enable MatchRegisterName to match register altnames

[Alex Bradbury via llvm-commits]

asb created this revision.
asb added reviewers: stoklund, adasgupt, grosbach.
asb added a subscriber: llvm-commits.

Currently Tablegen includes support for alternate register names, as added in r133940. These alternate names are made use of in the AsmWriter, but not in AsmMatcher. A number of in-tree targets have multiple names for register (e.g.  ABI and architectural names), but set ShouldEmitMatchRegisterName to false and write their own matching function, duplicating the information already available in Tablegen. This commit will cause the TableGen'ned MatchRegisterName function to match register altnames provided that MatchRegisterNameShouldMatchAltNames is set. This is set to false by default to ensure no unexpected changes to the behaviour of in-tree and out-of-tree targets, but I'd hope to later switch the default to true and remove the option altogether in the future.

This commit also modifies the doc comment for RegAltNameIndices to make it a little clearer, and removes altNameIndex from RegisterClass which is entirely unused.  

I wrote this for an out-of-tree target, but so that it can be tested I've optimistically enabled the functionality for the Hexagon backend (given that HexagonRegisterInfo.td specified alternate register names and AsmParsing support was very recently added, it seemed a good target).

Patch by Alex Bradbury.

http://reviews.llvm.org/D14994

Files:
  include/llvm/Target/Target.td
  lib/Target/Hexagon/Hexagon.td
  lib/Target/Hexagon/HexagonRegisterInfo.td
  lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h
  utils/TableGen/AsmMatcherEmitter.cpp

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