[PATCH] D13649: [mips] Clang ll/sc illegal instruction on mips64r2 with -O0

[Jelena Losic via llvm-commits]

Jelena.Losic added a comment.

Daniel,
could you please give me some opinion about the latest changes in this patch, is this ok?


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Comment at: test/CodeGen/Mips/atomicCmpSwapPW.ll:2
@@ +1,3 @@
+; RUN: llc  -O0 -march=mips64el -mcpu=mips64r2 < %s -filetype=asm -o - \
+; RUN:   | FileCheck %s -implicit-check-not=lw
+
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dsanders wrote:
> Could you add a comment explaining why this -implicit-check-not is the only check?
> 
> As far as I can see you're checking that we don't spill/reload using sw/lw.
I used -implicit-check-not just for lw, because after these changes in code llc doesn't emit any lw, but  in one line emits sw instruction(which is correct, but -implicit-check-not sw will cause test fail). 


http://reviews.llvm.org/D13649