[PATCH] D14719: Track pristine registers in terms of register units.

[Krzysztof Parzyszek via llvm-commits]

kparzysz created this revision.
kparzysz added reviewers: MatzeB, hfinkel.
kparzysz added a subscriber: llvm-commits.
kparzysz set the repository for this revision to rL LLVM.

Replace "getPristineRegs" with "getPristineRegUnits".

The set of pristine registers was calculated simply as the set difference between the callee-saved registers (TRI->getCalleeSavedRegs) and the actually saved registers (getCalleeSavedInfo).  The problem would arise, if these two sets were disjoint.  Hexagon lists the callee-saved registers as R16-R27, where each of there registers is a 32-bit registers. In most cases, the set of actually saved registers would be expressed in terms of register pairs (i.e. 64-bit registers) D8-D13. Each Dn consists of two Rn's, and from the architectural point of view the sets R16-R27 and D8-D13 are equivalent.  At the same time, in LLVM, Rn and Dn are formally different register sets, and the relationship between them will only be revealed to the users that explicitly query it.  The users that assume that the set of actually saved registers will be a subset of the callee-saved registers may perform incorrect actions.  In particular, the register scavenger would compute the set of available register units with that assumption, leading to a conclusion that all registers are pristine.  This would force the scavenger to use spill slots even when it is not necessary.

This change avoids the problem by tracking the pristine registers through the register units instead of the specific registers.

Repository:
  rL LLVM

http://reviews.llvm.org/D14719

Files:
  include/llvm/CodeGen/MachineFrameInfo.h
  lib/CodeGen/AggressiveAntiDepBreaker.cpp
  lib/CodeGen/CriticalAntiDepBreaker.cpp
  lib/CodeGen/LivePhysRegs.cpp
  lib/CodeGen/MachineFunction.cpp
  lib/CodeGen/MachineVerifier.cpp
  lib/CodeGen/RegisterScavenging.cpp
  lib/Target/ARM/ARMFrameLowering.cpp
  lib/Target/ARM/Thumb1FrameLowering.cpp

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