[PATCH] D14489: [AArch64] Applying load pair optimization for volatile load/store

[Tim Northover via llvm-commits]

t.p.northover added a comment.

Reordering the examples slightly:

> 3.Is this not safe ?




  ldr x9, [x0] (volatile)
  ldr x8, [x0, #8] (volatile) 
    ; into
  ldp x9, x8, [x0]

I think this is unsafe because the ldp can be interrupted after loading x9. It will then re-execute the entire instruction, causing 2 loads from [x0].

> 1.I guess this must be safe if ldp read [x0, #0] and then [x0, #8] ?




  ldr x9, [x0] 
  ldr x8, [x0, #8] (volatile) 
    ; into
  ldp x9, x8, [x0]

This is OK (assuming no atomics are around too). It's in-order and if the ldp is interrupted only x9 would be loaded twice, which isn't volatile so there's no problem repeating the access.

I'm really not sure it's worth bothering with though, generally either all or no accesses in some region are volatile (for accessing memory-mapped devices), so I rather doubt it would ever produce noticeable benefit.

> 2.Is this safe ?




  ldr x8, [x0, #8] (volatile) 
  ldr x9, [x0] 
    ; into
  ldp x9, x8, [x0]

This is also safe. You're allowed to reorder the loads since only one is volatile, and the volatile access ends up last in the ldp again, so re-executing would be harmless.

> 4.what about this case?




  ldr x9, [x0] 
  ldr x10, [x1]
  ldr x8, [x0, #8] (volatile) 
    ; into
  ldr x10, [x1]
  ldp x9, x8, [x0]

Also OK, again because the volatile access is last in the ldp.


http://reviews.llvm.org/D14489