[PATCH] D13161: [PATCH, PR24373] Combine shifts for x86

[Andrea Di Biagio via llvm-commits]

andreadb accepted this revision.
andreadb added a reviewer: andreadb.
andreadb added a comment.

The change looks good to me.

Thanks for measuring the performances after this change.
I agree with you that the poor codegen caused by a suboptimal scheduling of instructions in test 'load_sext_16i1_to_16i16' can be addressed by a later patch.
However, please file a bug for it so that we don't lose track of that problem.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:24427
@@ +24426,3 @@
+                         DAG.getConstant(-SarConst, DL, CVT));
+    else
+      return DAG.getNode(ISD::SRA, DL, VT, NN,
----------------
You can remove this else after return.


Repository:
  rL LLVM

http://reviews.llvm.org/D13161