[llvm] r252561 - [Hexagon] Fixing store instructions and reenabling a few more tests.
Colin LeMahieu via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 9 16:22:00 PST 2015
Author: colinl
Date: Mon Nov 9 18:22:00 2015
New Revision: 252561
URL: http://llvm.org/viewvc/llvm-project?rev=252561&view=rev
Log:
[Hexagon] Fixing store instructions and reenabling a few more tests.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
llvm/trunk/test/CodeGen/Hexagon/absimm.ll
llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll
llvm/trunk/test/MC/Disassembler/Hexagon/st.txt
llvm/trunk/test/MC/Hexagon/instructions/st.s
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=252561&r1=252560&r2=252561&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Mon Nov 9 18:22:00 2015
@@ -3320,9 +3320,9 @@ let isCall = 1, Uses = [R29, R31], isAsm
//===----------------------------------------------------------------------===//
let hasSideEffects = 0, isPredicable = 1 in
class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf>
- : STInst<(outs), (ins AddrOp:$addr, RC:$src),
- mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src"#!if(isHalf, ".h",""),
+ bits<2>MajOp, bit isAbs, bit isHalf>
+ : STInst<(outs), (ins ImmOp:$addr, RC:$src),
+ mnemonic # "(#$addr) = $src"#!if(isHalf, ".h",""),
[], "", V2LDST_tc_st_SLOT01> {
bits<19> addr;
bits<5> src;
@@ -3355,7 +3355,7 @@ class T_StoreAbsGP <string mnemonic, Reg
let hasSideEffects = 0, isPredicated = 1, opExtentBits = 6, opExtendable = 1 in
class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
bit isHalf, bit isNot, bit isNew>
- : STInst<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, RC: $src2),
+ : STInst<(outs), (ins PredRegs:$src1, u32MustExt:$absaddr, RC: $src2),
!if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
[], "", ST_tc_st_SLOT01>, AddrModeRel {
@@ -3387,7 +3387,7 @@ class T_StoreAbs_Pred <string mnemonic,
//===----------------------------------------------------------------------===//
class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
bits<2> MajOp, bit isHalf>
- : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1, isHalf>,
+ : T_StoreAbsGP <mnemonic, RC, u32MustExt, MajOp, 1, isHalf>,
AddrModeRel {
string ImmOpStr = !cast<string>(ImmOp);
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
@@ -3554,7 +3554,7 @@ defm storerf : ST_Abs <"memh", "STrif",
let isAsmParserOnly = 1 in
class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
- : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
+ : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, 0, isHalf> {
// Set BaseOpcode same as absolute addressing instructions so that
// non-predicated GP-Rel instructions can have relate with predicated
// Absolute instruction.
@@ -3569,7 +3569,7 @@ multiclass ST_GP <string mnemonic, strin
// Absolute instruction.
let BaseOpcode = BaseOp#_abs in {
def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
- globaladdress, 0, isHalf>;
+ 0, isHalf>;
// New-value store
def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
}
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=252561&r1=252560&r2=252561&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Mon Nov 9 18:22:00 2015
@@ -87,28 +87,23 @@ public:
StringRef Contents(Buffer);
auto PacketBundle = Contents.rsplit('\n');
auto HeadTail = PacketBundle.first.split('\n');
- auto Preamble = "\t{\n\t\t";
- auto Separator = "";
- while(!HeadTail.first.empty()) {
- OS << Separator;
- StringRef Inst;
+ StringRef Separator = "\n";
+ StringRef Indent = "\t\t";
+ OS << "\t{\n";
+ while (!HeadTail.first.empty()) {
+ StringRef InstTxt;
auto Duplex = HeadTail.first.split('\v');
- if(!Duplex.second.empty()){
- OS << Duplex.first << "\n";
- Inst = Duplex.second;
+ if (!Duplex.second.empty()) {
+ OS << Indent << Duplex.first << Separator;
+ InstTxt = Duplex.second;
+ } else if (!HeadTail.first.trim().startswith("immext")) {
+ InstTxt = Duplex.first;
}
- else {
- if(!HeadTail.first.startswith("immext"))
- Inst = Duplex.first;
- }
- OS << Preamble;
- OS << Inst;
+ if (!InstTxt.empty())
+ OS << Indent << InstTxt << Separator;
HeadTail = HeadTail.second.split('\n');
- Preamble = "";
- Separator = "\n\t\t";
}
- if(HexagonMCInstrInfo::bundleSize(Inst) != 0)
- OS << "\n\t}" << PacketBundle.second;
+ OS << "\t}" << PacketBundle.second;
}
};
}
Modified: llvm/trunk/test/CodeGen/Hexagon/absimm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/absimm.ll?rev=252561&r1=252560&r2=252561&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/absimm.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/absimm.ll Mon Nov 9 18:22:00 2015
@@ -1,7 +1,6 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that we generate absolute addressing mode instructions
; with immediate value.
-; XFAIL: *
define i32 @f1(i32 %i) nounwind {
; CHECK: memw(##786432){{ *}}={{ *}}r{{[0-9]+}}
Modified: llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll?rev=252561&r1=252560&r2=252561&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/zextloadi1.ll Mon Nov 9 18:22:00 2015
@@ -1,5 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; XFAIL: *
; CHECK: r{{[0-9]+}} = ##i129_l+16
; CHECK: r{{[0-9]+}} = ##i129_s+16
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/st.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/st.txt?rev=252561&r1=252560&r2=252561&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/st.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/st.txt Mon Nov 9 18:22:00 2015
@@ -1,6 +1,5 @@
# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
# Hexagon Programmer's Reference Manual 11.8 ST
-# XFAIL: *
# Store doubleword
0x9e 0xf5 0xd1 0x3b
Modified: llvm/trunk/test/MC/Hexagon/instructions/st.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/instructions/st.s?rev=252561&r1=252560&r2=252561&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/instructions/st.s (original)
+++ llvm/trunk/test/MC/Hexagon/instructions/st.s Mon Nov 9 18:22:00 2015
@@ -1,6 +1,5 @@
# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
# Hexagon Programmer's Reference Manual 11.8 ST
-# XFAIL: *
# Store doubleword
# CHECK: 9e f5 d1 3b
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