[llvm] r252519 - specify triple so Windows bots won't be sad

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Mon Nov  9 15:53:58 2015
New Revision: 252519

URL: http://llvm.org/viewvc/llvm-project?rev=252519&view=rev
Log:
specify triple so Windows bots won't be sad

Modified:
    llvm/trunk/test/CodeGen/X86/x86-64-double-precision-shift-left.ll
    llvm/trunk/test/CodeGen/X86/x86-64-double-precision-shift-right.ll

Modified: llvm/trunk/test/CodeGen/X86/x86-64-double-precision-shift-left.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-double-precision-shift-left.ll?rev=252519&r1=252518&r2=252519&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-64-double-precision-shift-left.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-64-double-precision-shift-left.ll Mon Nov  9 15:53:58 2015
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s
 ; Verify that for the architectures that are known to have poor latency
 ; double precision shift instructions we generate alternative sequence 
 ; of instructions with lower latencies instead of shld instruction.

Modified: llvm/trunk/test/CodeGen/X86/x86-64-double-precision-shift-right.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-double-precision-shift-right.ll?rev=252519&r1=252518&r2=252519&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-64-double-precision-shift-right.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-64-double-precision-shift-right.ll Mon Nov  9 15:53:58 2015
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s
 ; Verify that for the architectures that are known to have poor latency
 ; double precision shift instructions we generate alternative sequence 
 ; of instructions with lower latencies instead of shrd instruction.