[PATCH] D14142: [2/4] Allow SP in rGPR, starting from ARMv8 (assembly)

[A. Skrobov via llvm-commits]

tyomitch created this revision.
tyomitch added reviewers: jmolloy, rengolin.
tyomitch added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

http://reviews.llvm.org/D14142

Files:
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  test/MC/ARM/basic-thumb2-instructions-v8.s

Index: test/MC/ARM/basic-thumb2-instructions-v8.s
===================================================================
--- test/MC/ARM/basic-thumb2-instructions-v8.s
+++ test/MC/ARM/basic-thumb2-instructions-v8.s
@@ -24,6 +24,17 @@
 @ CHECK-V8: hlt #24                       @ encoding: [0x98,0xba]
 @ CHECK-V7: error: instruction requires: armv8
 
+@ Can accept SP as rGPR
+        sbc.w r6, r3, sp, asr #16
+        and.w r6, r3, sp, asr #16
+        and sp, r0, #0
+@ CHECK-V8: sbc.w r6, r3, sp, asr #16     @ encoding: [0x63,0xeb,0x2d,0x46]
+@ CHECK-V8: and.w r6, r3, sp, asr #16     @ encoding: [0x03,0xea,0x2d,0x46]
+@ CHECK-V8: and   sp, r0, #0              @ encoding: [0x00,0xf0,0x00,0x0d]
+@ CHECK-V7: error: using SP in this instruction requires ARMv8 or later
+@ CHECK-V7: error: using SP in this instruction requires ARMv8 or later
+@ CHECK-V7: error: invalid operand for instruction
+
 @ DCPS{1,2,3}
         dcps1
         dcps2
Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -10011,6 +10011,10 @@
              "expression value must be representable in 32 bits");
     }
     break;
+  case MCK_rGPR:
+    if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
+      return Match_Success;
+    break;
   case MCK_GPRPair:
     if (Op.isReg() &&
         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))


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