[llvm] r251230 - [X86] PMOV*X* tests - remove unnecessary mcpu arguments and regenerate
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 25 04:55:10 PDT 2015
Author: rksimon
Date: Sun Oct 25 06:55:10 2015
New Revision: 251230
URL: http://llvm.org/viewvc/llvm-project?rev=251230&view=rev
Log:
[X86] PMOV*X* tests - remove unnecessary mcpu arguments and regenerate
Modified:
llvm/trunk/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll
Modified: llvm/trunk/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll?rev=251230&r1=251229&r2=251230&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll Sun Oct 25 06:55:10 2015
@@ -1,10 +1,16 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
define <8 x i16> @test_llvm_x86_sse41_pmovsxbw(<16 x i8>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovsxbw
-; SSE41: pmovsxbw (%rdi), %xmm0
-; AVX: vpmovsxbw (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbw:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovsxbw (%rdi), %xmm0
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovsxbw:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxbw (%rdi), %xmm0
+; AVX-NEXT: retq
%1 = load <16 x i8>, <16 x i8>* %a, align 1
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%3 = sext <8 x i8> %2 to <8 x i16>
@@ -12,9 +18,15 @@ define <8 x i16> @test_llvm_x86_sse41_pm
}
define <4 x i32> @test_llvm_x86_sse41_pmovsxbd(<16 x i8>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovsxbd
-; SSE41: pmovsxbd (%rdi), %xmm0
-; AVX: vpmovsxbd (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbd:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovsxbd (%rdi), %xmm0
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovsxbd:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
+; AVX-NEXT: retq
%1 = load <16 x i8>, <16 x i8>* %a, align 1
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = sext <4 x i8> %2 to <4 x i32>
@@ -22,9 +34,15 @@ define <4 x i32> @test_llvm_x86_sse41_pm
}
define <2 x i64> @test_llvm_x86_sse41_pmovsxbq(<16 x i8>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovsxbq
-; SSE41: pmovsxbq (%rdi), %xmm0
-; AVX: vpmovsxbq (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbq:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovsxbq (%rdi), %xmm0
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovsxbq:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxbq (%rdi), %xmm0
+; AVX-NEXT: retq
%1 = load <16 x i8>, <16 x i8>* %a, align 1
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
%3 = sext <2 x i8> %2 to <2 x i64>
@@ -32,9 +50,15 @@ define <2 x i64> @test_llvm_x86_sse41_pm
}
define <4 x i32> @test_llvm_x86_sse41_pmovsxwd(<8 x i16>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovsxwd
-; SSE41: pmovsxwd (%rdi), %xmm0
-; AVX: vpmovsxwd (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwd:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovsxwd (%rdi), %xmm0
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovsxwd:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
+; AVX-NEXT: retq
%1 = load <8 x i16>, <8 x i16>* %a, align 1
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = sext <4 x i16> %2 to <4 x i32>
@@ -42,9 +66,15 @@ define <4 x i32> @test_llvm_x86_sse41_pm
}
define <2 x i64> @test_llvm_x86_sse41_pmovsxwq(<8 x i16>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovsxwq
-; SSE41: pmovsxwq (%rdi), %xmm0
-; AVX: vpmovsxwq (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwq:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovsxwq (%rdi), %xmm0
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovsxwq:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxwq (%rdi), %xmm0
+; AVX-NEXT: retq
%1 = load <8 x i16>, <8 x i16>* %a, align 1
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
%3 = sext <2 x i16> %2 to <2 x i64>
@@ -52,9 +82,15 @@ define <2 x i64> @test_llvm_x86_sse41_pm
}
define <2 x i64> @test_llvm_x86_sse41_pmovsxdq(<4 x i32>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovsxdq
-; SSE41: pmovsxdq (%rdi), %xmm0
-; AVX: vpmovsxdq (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovsxdq:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovsxdq (%rdi), %xmm0
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovsxdq:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovsxdq (%rdi), %xmm0
+; AVX-NEXT: retq
%1 = load <4 x i32>, <4 x i32>* %a, align 1
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
%3 = sext <2 x i32> %2 to <2 x i64>
@@ -62,54 +98,90 @@ define <2 x i64> @test_llvm_x86_sse41_pm
}
define <8 x i16> @test_llvm_x86_sse41_pmovzxbw(<16 x i8>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovzxbw
-; SSE41: pmovzxbw (%rdi), %xmm0
-; AVX: vpmovzxbw (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbw:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovzxbw:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
+; AVX-NEXT: retq
%1 = load <16 x i8>, <16 x i8>* %a, align 1
%2 = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %1)
ret <8 x i16> %2
}
define <4 x i32> @test_llvm_x86_sse41_pmovzxbd(<16 x i8>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovzxbd
-; SSE41: pmovzxbd (%rdi), %xmm0
-; AVX: vpmovzxbd (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbd:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovzxbd:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX-NEXT: retq
%1 = load <16 x i8>, <16 x i8>* %a, align 1
%2 = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %1)
ret <4 x i32> %2
}
define <2 x i64> @test_llvm_x86_sse41_pmovzxbq(<16 x i8>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovzxbq
-; SSE41: pmovzxbq (%rdi), %xmm0
-; AVX: vpmovzxbq (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbq:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovzxbq:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
+; AVX-NEXT: retq
%1 = load <16 x i8>, <16 x i8>* %a, align 1
%2 = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %1)
ret <2 x i64> %2
}
define <4 x i32> @test_llvm_x86_sse41_pmovzxwd(<8 x i16>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovzxwd
-; SSE41: pmovzxwd (%rdi), %xmm0
-; AVX: vpmovzxwd (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwd:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovzxwd:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; AVX-NEXT: retq
%1 = load <8 x i16>, <8 x i16>* %a, align 1
%2 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %1)
ret <4 x i32> %2
}
define <2 x i64> @test_llvm_x86_sse41_pmovzxwq(<8 x i16>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovzxwq
-; SSE41: pmovzxwq (%rdi), %xmm0
-; AVX: vpmovzxwq (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwq:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovzxwq:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
+; AVX-NEXT: retq
%1 = load <8 x i16>, <8 x i16>* %a, align 1
%2 = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %1)
ret <2 x i64> %2
}
define <2 x i64> @test_llvm_x86_sse41_pmovzxdq(<4 x i32>* %a) {
-; CHECK-LABEL: test_llvm_x86_sse41_pmovzxdq
-; SSE41: pmovzxdq (%rdi), %xmm0
-; AVX: vpmovzxdq (%rdi), %xmm0
+; SSE41-LABEL: test_llvm_x86_sse41_pmovzxdq:
+; SSE41: ## BB#0:
+; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
+; SSE41-NEXT: retq
+;
+; AVX-LABEL: test_llvm_x86_sse41_pmovzxdq:
+; AVX: ## BB#0:
+; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
+; AVX-NEXT: retq
%1 = load <4 x i32>, <4 x i32>* %a, align 1
%2 = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %1)
ret <2 x i64> %2
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