[llvm] r250961 - AMDGPU: Fix adding redundant m0 uses

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed Oct 21 17:37:51 2015
New Revision: 250961

URL: http://llvm.org/viewvc/llvm-project?rev=250961&view=rev
Log:
AMDGPU: Fix adding redundant m0 uses

BuildMI already adds these since they are defined correctly now.

Modified:
    llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp?rev=250961&r1=250960&r2=250961&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp Wed Oct 21 17:37:51 2015
@@ -438,7 +438,6 @@ void SILowerControlFlowPass::IndirectSrc
   MachineInstr *MovRel =
     BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
             .addReg(Reg)
-            .addReg(AMDGPU::M0, RegState::Implicit)
             .addReg(Vec, RegState::Implicit);
 
   LoadM0(MI, MovRel, Off);
@@ -460,7 +459,6 @@ void SILowerControlFlowPass::IndirectDst
     BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
             .addReg(Reg, RegState::Define)
             .addReg(Val)
-            .addReg(AMDGPU::M0, RegState::Implicit)
             .addReg(Dst, RegState::Implicit);
 
   LoadM0(MI, MovRel, Off);