[PATCH] D13737: AMDGPU: Fix asserts on invalid register ranges

[Nicolai Hähnle via llvm-commits]

nhaehnle added a subscriber: nhaehnle.

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Comment at: lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:543-548
@@ -542,4 +542,8 @@
     } else {
       // SGPR registers are aligned.  Max alignment is 4 dwords.
-      RegIndexInClass = RegLo / std::min(RegWidth, 4u);
+      unsigned Size = std::min(RegWidth, 4u);
+      if (RegLo % Size != 0)
+        return true;
+
+      RegIndexInClass = RegLo / Size;
     }
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Nitpick: Maybe rename Size to Alignment?


http://reviews.llvm.org/D13737