[llvm] r250434 - [SelectionDAG] Remove dead code. NFC.
Owen Anderson via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 19 11:18:20 PDT 2015
My backends use SelectionDAG::getTargetIndex() a lot...
—Owen
> On Oct 15, 2015, at 10:54 AM, Benjamin Kramer via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>
> Author: d0k
> Date: Thu Oct 15 12:54:06 2015
> New Revision: 250434
>
> URL: http://llvm.org/viewvc/llvm-project?rev=250434&view=rev
> Log:
> [SelectionDAG] Remove dead code. NFC.
>
> Carefully selected parts without deleting graph stuff and dumping methods.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/FastISel.h
> llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
>
> Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=250434&r1=250433&r2=250434&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Thu Oct 15 12:54:06 2015
> @@ -425,12 +425,6 @@ protected:
> const TargetRegisterClass *RC,
> const ConstantFP *FPImm);
>
> - /// \brief Emit a MachineInstr with one register operand, a floating point
> - /// immediate, and a result register in the given register class.
> - unsigned fastEmitInst_rf(unsigned MachineInstOpcode,
> - const TargetRegisterClass *RC, unsigned Op0,
> - bool Op0IsKill, const ConstantFP *FPImm);
> -
> /// \brief Emit a MachineInstr with two register operands, an immediate, and a
> /// result register in the given register class.
> unsigned fastEmitInst_rri(unsigned MachineInstOpcode,
> @@ -438,23 +432,11 @@ protected:
> bool Op0IsKill, unsigned Op1, bool Op1IsKill,
> uint64_t Imm);
>
> - /// \brief Emit a MachineInstr with two register operands, two immediates
> - /// operands, and a result register in the given register class.
> - unsigned fastEmitInst_rrii(unsigned MachineInstOpcode,
> - const TargetRegisterClass *RC, unsigned Op0,
> - bool Op0IsKill, unsigned Op1, bool Op1IsKill,
> - uint64_t Imm1, uint64_t Imm2);
> -
> /// \brief Emit a MachineInstr with a single immediate operand, and a result
> /// register in the given register class.
> unsigned fastEmitInst_i(unsigned MachineInstrOpcode,
> const TargetRegisterClass *RC, uint64_t Imm);
>
> - /// \brief Emit a MachineInstr with a two immediate operands.
> - unsigned fastEmitInst_ii(unsigned MachineInstrOpcode,
> - const TargetRegisterClass *RC, uint64_t Imm1,
> - uint64_t Imm2);
> -
> /// \brief Emit a MachineInstr for an extract_subreg from a specified index of
> /// a superregister to a specified type.
> unsigned fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=250434&r1=250433&r2=250434&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Oct 15 12:54:06 2015
> @@ -82,11 +82,6 @@ namespace ISD {
> /// all ConstantFPSDNode or undef.
> bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
>
> - /// Return true if the specified node is a
> - /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
> - /// element is not an undef.
> - bool isScalarToVector(const SDNode *N);
> -
> /// Return true if the node has at least one operand
> /// and all operands of the specified node are ISD::UNDEF.
> bool allOperandsUndef(const SDNode *N);
> @@ -676,22 +671,6 @@ public:
> return nullptr;
> }
>
> - // If this is a pseudo op, like copyfromreg, look to see if there is a
> - // real target node glued to it. If so, return the target node.
> - const SDNode *getGluedMachineNode() const {
> - const SDNode *FoundNode = this;
> -
> - // Climb up glue edges until a machine-opcode node is found, or the
> - // end of the chain is reached.
> - while (!FoundNode->isMachineOpcode()) {
> - const SDNode *N = FoundNode->getGluedNode();
> - if (!N) break;
> - FoundNode = N;
> - }
> -
> - return FoundNode;
> - }
> -
> /// If this node has a glue value with a user, return
> /// the user (there is at most one). Otherwise return NULL.
> SDNode *getGluedUser() const {
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=250434&r1=250433&r2=250434&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Oct 15 12:54:06 2015
> @@ -1895,28 +1895,6 @@ unsigned FastISel::fastEmitInst_f(unsign
> return ResultReg;
> }
>
> -unsigned FastISel::fastEmitInst_rf(unsigned MachineInstOpcode,
> - const TargetRegisterClass *RC, unsigned Op0,
> - bool Op0IsKill, const ConstantFP *FPImm) {
> - const MCInstrDesc &II = TII.get(MachineInstOpcode);
> -
> - unsigned ResultReg = createResultReg(RC);
> - Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
> -
> - if (II.getNumDefs() >= 1)
> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
> - .addReg(Op0, getKillRegState(Op0IsKill))
> - .addFPImm(FPImm);
> - else {
> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
> - .addReg(Op0, getKillRegState(Op0IsKill))
> - .addFPImm(FPImm);
> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
> - TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
> - }
> - return ResultReg;
> -}
> -
> unsigned FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
> const TargetRegisterClass *RC, unsigned Op0,
> bool Op0IsKill, unsigned Op1,
> @@ -1943,35 +1921,6 @@ unsigned FastISel::fastEmitInst_rri(unsi
> return ResultReg;
> }
>
> -unsigned FastISel::fastEmitInst_rrii(unsigned MachineInstOpcode,
> - const TargetRegisterClass *RC,
> - unsigned Op0, bool Op0IsKill, unsigned Op1,
> - bool Op1IsKill, uint64_t Imm1,
> - uint64_t Imm2) {
> - const MCInstrDesc &II = TII.get(MachineInstOpcode);
> -
> - unsigned ResultReg = createResultReg(RC);
> - Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
> - Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
> -
> - if (II.getNumDefs() >= 1)
> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
> - .addReg(Op0, getKillRegState(Op0IsKill))
> - .addReg(Op1, getKillRegState(Op1IsKill))
> - .addImm(Imm1)
> - .addImm(Imm2);
> - else {
> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
> - .addReg(Op0, getKillRegState(Op0IsKill))
> - .addReg(Op1, getKillRegState(Op1IsKill))
> - .addImm(Imm1)
> - .addImm(Imm2);
> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
> - TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
> - }
> - return ResultReg;
> -}
> -
> unsigned FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
> const TargetRegisterClass *RC, uint64_t Imm) {
> unsigned ResultReg = createResultReg(RC);
> @@ -1985,25 +1934,6 @@ unsigned FastISel::fastEmitInst_i(unsign
> BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
> TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
> }
> - return ResultReg;
> -}
> -
> -unsigned FastISel::fastEmitInst_ii(unsigned MachineInstOpcode,
> - const TargetRegisterClass *RC, uint64_t Imm1,
> - uint64_t Imm2) {
> - unsigned ResultReg = createResultReg(RC);
> - const MCInstrDesc &II = TII.get(MachineInstOpcode);
> -
> - if (II.getNumDefs() >= 1)
> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
> - .addImm(Imm1)
> - .addImm(Imm2);
> - else {
> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm1)
> - .addImm(Imm2);
> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
> - TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
> - }
> return ResultReg;
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=250434&r1=250433&r2=250434&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu Oct 15 12:54:06 2015
> @@ -1768,12 +1768,6 @@ void DAGTypeLegalizer::ExpandIntRes_ADDS
> ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
> }
>
> -void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
> - SDValue &Lo, SDValue &Hi) {
> - SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
> - SplitInteger(Res, Lo, Hi);
> -}
> -
> void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
> SDValue &Lo, SDValue &Hi) {
> EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=250434&r1=250433&r2=250434&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Thu Oct 15 12:54:06 2015
> @@ -276,7 +276,6 @@ private:
> SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
> SDValue PromoteIntOp_CONVERT_RNDSAT(SDNode *N);
> SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
> - SDValue PromoteIntOp_EXTRACT_ELEMENT(SDNode *N);
> SDValue PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N);
> SDValue PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N);
> SDValue PromoteIntOp_CONCAT_VECTORS(SDNode *N);
> @@ -284,7 +283,6 @@ private:
> SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
> SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
> SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
> - SDValue PromoteIntOp_VSETCC(SDNode *N, unsigned OpNo);
> SDValue PromoteIntOp_Shift(SDNode *N);
> SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
> SDValue PromoteIntOp_SINT_TO_FP(SDNode *N);
> @@ -312,8 +310,6 @@ private:
>
> // Integer Result Expansion.
> void ExpandIntegerResult(SDNode *N, unsigned ResNo);
> - void ExpandIntRes_MERGE_VALUES (SDNode *N, unsigned ResNo,
> - SDValue &Lo, SDValue &Hi);
> void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
> void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi);
> void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
> @@ -355,10 +351,7 @@ private:
>
> // Integer Operand Expansion.
> bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo);
> - SDValue ExpandIntOp_BITCAST(SDNode *N);
> SDValue ExpandIntOp_BR_CC(SDNode *N);
> - SDValue ExpandIntOp_BUILD_VECTOR(SDNode *N);
> - SDValue ExpandIntOp_EXTRACT_ELEMENT(SDNode *N);
> SDValue ExpandIntOp_SELECT_CC(SDNode *N);
> SDValue ExpandIntOp_SETCC(SDNode *N);
> SDValue ExpandIntOp_Shift(SDNode *N);
> @@ -576,7 +569,6 @@ private:
> SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
> SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
> SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
> - SDValue ScalarizeVecRes_SIGN_EXTEND_INREG(SDNode *N);
> SDValue ScalarizeVecRes_VSELECT(SDNode *N);
> SDValue ScalarizeVecRes_SELECT(SDNode *N);
> SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
> @@ -618,7 +610,6 @@ private:
> void SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi);
>
> void SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi);
> - void SplitVecRes_BUILD_PAIR(SDNode *N, SDValue &Lo, SDValue &Hi);
> void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
> void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
> void SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
> @@ -630,9 +621,7 @@ private:
> void SplitVecRes_MLOAD(MaskedLoadSDNode *N, SDValue &Lo, SDValue &Hi);
> void SplitVecRes_MGATHER(MaskedGatherSDNode *N, SDValue &Lo, SDValue &Hi);
> void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
> - void SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi);
> void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
> - void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
> void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
> SDValue &Hi);
>
> @@ -684,7 +673,6 @@ private:
> SDValue WidenVecRes_LOAD(SDNode* N);
> SDValue WidenVecRes_MLOAD(MaskedLoadSDNode* N);
> SDValue WidenVecRes_SCALAR_TO_VECTOR(SDNode* N);
> - SDValue WidenVecRes_SIGN_EXTEND_INREG(SDNode* N);
> SDValue WidenVecRes_SELECT(SDNode* N);
> SDValue WidenVecRes_SELECT_CC(SDNode* N);
> SDValue WidenVecRes_SETCC(SDNode* N);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h?rev=250434&r1=250433&r2=250434&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h Thu Oct 15 12:54:06 2015
> @@ -86,12 +86,6 @@ namespace llvm {
> /// flagged together nodes with a single SUnit.
> void BuildSchedGraph(AliasAnalysis *AA);
>
> - /// InitVRegCycleFlag - Set isVRegCycle if this node's single use is
> - /// CopyToReg and its only active data operands are CopyFromReg within a
> - /// single block loop.
> - ///
> - void InitVRegCycleFlag(SUnit *SU);
> -
> /// InitNumRegDefsLeft - Determine the # of regs defined by this node.
> ///
> void InitNumRegDefsLeft(SUnit *SU);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=250434&r1=250433&r2=250434&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Oct 15 12:54:06 2015
> @@ -211,28 +211,6 @@ bool ISD::isBuildVectorOfConstantFPSDNod
> return true;
> }
>
> -/// isScalarToVector - Return true if the specified node is a
> -/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
> -/// element is not an undef.
> -bool ISD::isScalarToVector(const SDNode *N) {
> - if (N->getOpcode() == ISD::SCALAR_TO_VECTOR)
> - return true;
> -
> - if (N->getOpcode() != ISD::BUILD_VECTOR)
> - return false;
> - if (N->getOperand(0).getOpcode() == ISD::UNDEF)
> - return false;
> - unsigned NumElems = N->getNumOperands();
> - if (NumElems == 1)
> - return false;
> - for (unsigned i = 1; i < NumElems; ++i) {
> - SDValue V = N->getOperand(i);
> - if (V.getOpcode() != ISD::UNDEF)
> - return false;
> - }
> - return true;
> -}
> -
> /// allOperandsUndef - Return true if the node has at least one operand
> /// and all operands of the specified node are ISD::UNDEF.
> bool ISD::allOperandsUndef(const SDNode *N) {
> @@ -1418,24 +1396,6 @@ SDValue SelectionDAG::getConstantPool(Ma
> CSEMap.InsertNode(N, IP);
> InsertNode(N);
> return SDValue(N, 0);
> -}
> -
> -SDValue SelectionDAG::getTargetIndex(int Index, EVT VT, int64_t Offset,
> - unsigned char TargetFlags) {
> - FoldingSetNodeID ID;
> - AddNodeIDNode(ID, ISD::TargetIndex, getVTList(VT), None);
> - ID.AddInteger(Index);
> - ID.AddInteger(Offset);
> - ID.AddInteger(TargetFlags);
> - void *IP = nullptr;
> - if (SDNode *E = FindNodeOrInsertPos(ID, IP))
> - return SDValue(E, 0);
> -
> - SDNode *N = new (NodeAllocator) TargetIndexSDNode(Index, VT, Offset,
> - TargetFlags);
> - CSEMap.InsertNode(N, IP);
> - InsertNode(N);
> - return SDValue(N, 0);
> }
>
> SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=250434&r1=250433&r2=250434&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Thu Oct 15 12:54:06 2015
> @@ -597,10 +597,6 @@ public:
> ///
> FunctionLoweringInfo &FuncInfo;
>
> - /// OptLevel - What optimization level we're generating code for.
> - ///
> - CodeGenOpt::Level OptLevel;
> -
> /// GFI - Garbage collection metadata for the function.
> GCFunctionInfo *GFI;
>
> @@ -618,7 +614,7 @@ public:
> SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
> CodeGenOpt::Level ol)
> : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
> - DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
> + DAG(dag), FuncInfo(funcinfo),
> HasTailCall(false) {
> }
>
>
>
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