[llvm] r250685 - [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions

Zlatko Buljan via llvm-commits llvm-commits at lists.llvm.org
Mon Oct 19 00:16:26 PDT 2015


Author: zbuljan
Date: Mon Oct 19 02:16:26 2015
New Revision: 250685

URL: http://llvm.org/viewvc/llvm-project?rev=250685&view=rev
Log:
[mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions
Differential Revision: http://reviews.llvm.org/D13130

Modified:
    llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td
    llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td
    llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
    llvm/trunk/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
    llvm/trunk/test/MC/Mips/micromips-dsp/valid.s
    llvm/trunk/test/MC/Mips/micromips-dspr2/valid.s

Modified: llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td?rev=250685&r1=250684&r2=250685&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td Mon Oct 19 02:16:26 2015
@@ -64,3 +64,16 @@ class POOL32A_2RAC_FMT<string opstr, bit
   let Inst{13-6}  = op;
   let Inst{5-0}   = 0b111100;
 }
+
+class POOL32A_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
+  bits<5> rd;
+  bits<5> rs;
+  bits<5> rt;
+
+  let Inst{31-26} = 0b000000;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = rd;
+  let Inst{10}    = 0b0;
+  let Inst{9-0}   = op;
+}

Modified: llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td?rev=250685&r1=250684&r2=250685&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td Mon Oct 19 02:16:26 2015
@@ -12,7 +12,21 @@
 //===----------------------------------------------------------------------===//
 
 // Instruction encoding.
+class ADDQ_PH_MM_ENC : POOL32A_3R_FMT<"addq.ph", 0b00000001101>;
+class ADDQ_S_PH_MM_ENC : POOL32A_3R_FMT<"addq_s.ph", 0b10000001101>;
+class ADDQ_S_W_MM_ENC : POOL32A_3RB0_FMT<"addq_s.w", 0b1100000101>;
+class ADDQH_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh.ph", 0b00001001101>;
+class ADDQH_R_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.ph", 0b10001001101>;
+class ADDQH_W_MMR2_ENC: POOL32A_3R_FMT<"addqh.w", 0b00010001101>;
+class ADDQH_R_W_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.w", 0b10010001101>;
+class ADDU_PH_MMR2_ENC : POOL32A_3R_FMT<"addu.ph", 0b00100001101>;
+class ADDU_S_PH_MMR2_ENC : POOL32A_3R_FMT<"addu_s.ph", 0b10100001101>;
 class ADDU_QB_MM_ENC : POOL32A_3R_FMT<"addu.qb", 0b00011001101>;
+class ADDU_S_QB_MM_ENC : POOL32A_3R_FMT<"addu_s.qb", 0b10011001101>;
+class ADDUH_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh.qb", 0b00101001101>;
+class ADDUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh_r.qb", 0b10101001101>;
+class ADDSC_MM_ENC : POOL32A_3RB0_FMT<"addsc", 0b1110000101>;
+class ADDWC_MM_ENC : POOL32A_3RB0_FMT<"addwc", 0b1111000101>;
 class DPA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpa.w.ph", 0b00000010>;
 class DPAQ_S_W_PH_MM_ENC : POOL32A_AC2R_FMT<"dpaq_s.w.ph", 0b00001010>;
 class DPAQ_SA_L_W_MM_ENC : POOL32A_AC2R_FMT<"dpaq_sa.l.w", 0b01001010>;
@@ -50,18 +64,17 @@ class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM
   "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
 
 // microMIPS DSP Rev 1
+def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
+def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC;
+def ADDQ_S_W_MM : DspMMRel, ADDQ_S_W_MM_ENC, ADDQ_S_W_DESC;
 def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC;
+def ADDU_S_QB_MM : DspMMRel, ADDU_S_QB_MM_ENC, ADDU_S_QB_DESC;
+def ADDSC_MM : DspMMRel, ADDSC_MM_ENC, ADDSC_DESC;
+def ADDWC_MM : DspMMRel, ADDWC_MM_ENC, ADDWC_DESC;
 def DPAQ_S_W_PH_MM : DspMMRel, DPAQ_S_W_PH_MM_ENC, DPAQ_S_W_PH_DESC;
 def DPAQ_SA_L_W_MM : DspMMRel, DPAQ_SA_L_W_MM_ENC, DPAQ_SA_L_W_DESC;
 def DPAU_H_QBL_MM : DspMMRel, DPAU_H_QBL_MM_ENC, DPAU_H_QBL_DESC;
 def DPAU_H_QBR_MM : DspMMRel, DPAU_H_QBR_MM_ENC, DPAU_H_QBR_DESC;
-// microMIPS DSP Rev 2
-def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2;
-def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
-                        ISA_DSPR2;
-def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
-                         ISA_DSPR2;
-def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
 def ABSQ_S_PH_MM : DspMMRel, ABSQ_S_PH_MM_ENC, ABSQ_S_PH_MM_DESC;
 def ABSQ_S_W_MM : DspMMRel, ABSQ_S_W_MM_ENC, ABSQ_S_W_MM_DESC;
 def INSV_MM : DspMMRel, INSV_MM_ENC, INSV_DESC;
@@ -74,3 +87,17 @@ def MULTU_DSP_MM : DspMMRel, MULTU_DSP_M
 // microMIPS DSP Rev 2
 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
                      ISA_DSPR2;
+def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2;
+def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
+def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2;
+def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
+def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2;
+def ADDU_S_PH_MMR2 : DspMMRel, ADDU_S_PH_MMR2_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
+def ADDUH_QB_MMR2 : DspMMRel, ADDUH_QB_MMR2_ENC, ADDUH_QB_DESC, ISA_DSPR2;
+def ADDUH_R_QB_MMR2 : DspMMRel, ADDUH_R_QB_MMR2_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
+def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2;
+def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
+                        ISA_DSPR2;
+def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
+                         ISA_DSPR2;
+def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;

Modified: llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td?rev=250685&r1=250684&r2=250685&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td Mon Oct 19 02:16:26 2015
@@ -365,6 +365,7 @@ class ADDUH_QB_DESC_BASE<string instr_as
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
   InstrItinClass Itinerary = itin;
+  string BaseOpcode = instr_asm;
 }
 
 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@@ -1079,17 +1080,17 @@ def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DE
 // Instruction defs.
 // MIPS DSP Rev 1
 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
-def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
+def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
-def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
-def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
+def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
+def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
-def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
+def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
-def ADDSC : ADDSC_ENC, ADDSC_DESC;
-def ADDWC : ADDWC_ENC, ADDWC_DESC;
+def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
+def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
 def MODSUB : MODSUB_ENC, MODSUB_DESC;
 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
@@ -1195,24 +1196,24 @@ def WRDSP : WRDSP_ENC, WRDSP_DESC;
 // MIPS DSP Rev 2
 let Predicates = [HasDSPR2] in {
 
-def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
-def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
+def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
+def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
-def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
-def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
+def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
+def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
-def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
-def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
+def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
+def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
-def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
-def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
+def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
+def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;

Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt?rev=250685&r1=250684&r2=250685&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt Mon Oct 19 02:16:26 2015
@@ -1,6 +1,12 @@
 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips  -mattr=+dsp | FileCheck %s
 
 0x00 0xa4 0x18 0xcd # CHECK: addu.qb $3, $4, $5
+0x00 0xa4 0x1c 0xcd # CHECK: addu_s.qb $3, $4, $5
+0x00 0xa4 0x1b 0x85 # CHECK: addsc $3, $4, $5
+0x00 0xa4 0x1b 0xc5 # CHECK: addwc $3, $4, $5
+0x00 0xa4 0x18 0x0d # CHECK: addq.ph $3, $4, $5
+0x00 0xa4 0x1c 0x0d # CHECK: addq_s.ph $3, $4, $5
+0x00 0xa4 0x1b 0x05 # CHECK: addq_s.w $3, $4, $5
 0x00 0x65 0x42 0xbc # CHECK: dpaq_s.w.ph $ac1, $5, $3
 0x00 0x64 0x92 0xbc # CHECK: dpaq_sa.l.w $ac2, $4, $3
 0x00 0x83 0x60 0xbc # CHECK: dpau.h.qbl $ac1, $3, $4

Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt?rev=250685&r1=250684&r2=250685&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt Mon Oct 19 02:16:26 2015
@@ -1,5 +1,13 @@
 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
 
+0x00 0xa4 0x18 0x4d # CHECK: addqh.ph $3, $4, $5
+0x00 0xa4 0x1c 0x4d # CHECK: addqh_r.ph $3, $4, $5
+0x00 0xa4 0x18 0x8d # CHECK: addqh.w $3, $4, $5
+0x00 0xa4 0x1c 0x8d # CHECK: addqh_r.w $3, $4, $5
+0x00 0xa4 0x19 0x0d # CHECK: addu.ph $3, $4, $5
+0x00 0xa4 0x1d 0x0d # CHECK: addu_s.ph $3, $4, $5
+0x00 0xa4 0x19 0x4d # CHECK: adduh.qb $3, $4, $5
+0x00 0xa4 0x1d 0x4d # CHECK: adduh_r.qb $3, $4, $5
 0x00 0x64 0x01 0x3c # CHECK: absq_s.qb $3, $4
 0x00 0x43 0x00 0xbc # CHECK: dpa.w.ph $ac0, $3, $2
 0x00 0xec 0xe2 0xbc # CHECK: dpaqx_s.w.ph $ac3, $12, $7

Modified: llvm/trunk/test/MC/Mips/micromips-dsp/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-dsp/valid.s?rev=250685&r1=250684&r2=250685&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-dsp/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-dsp/valid.s Mon Oct 19 02:16:26 2015
@@ -2,6 +2,12 @@
 
   .set noat
   addu.qb $3, $4, $5           # CHECK: addu.qb $3, $4, $5      # encoding: [0x00,0xa4,0x18,0xcd]
+  addu_s.qb $3, $4, $5         # CHECK: addu_s.qb $3, $4, $5    # encoding: [0x00,0xa4,0x1c,0xcd]
+  addsc $3, $4, $5             # CHECK: addsc $3, $4, $5        # encoding: [0x00,0xa4,0x1b,0x85]
+  addwc $3, $4, $5             # CHECK: addwc $3, $4, $5        # encoding: [0x00,0xa4,0x1b,0xc5]
+  addq.ph $3, $4, $5           # CHECK: addq.ph $3, $4, $5      # encoding: [0x00,0xa4,0x18,0x0d]
+  addq_s.ph $3, $4, $5         # CHECK: addq_s.ph $3, $4, $5    # encoding: [0x00,0xa4,0x1c,0x0d]
+  addq_s.w $3, $4, $5          # CHECK: addq_s.w $3, $4, $5     # encoding: [0x00,0xa4,0x1b,0x05]
   dpaq_s.w.ph $ac1, $5, $3     # CHECK: dpaq_s.w.ph $ac1, $5, $3   # encoding: [0x00,0x65,0x42,0xbc]
   dpaq_sa.l.w $ac2, $4, $3     # CHECK: dpaq_sa.l.w $ac2, $4, $3   # encoding: [0x00,0x64,0x92,0xbc]
   dpau.h.qbl $ac1, $3, $4      # CHECK: dpau.h.qbl $ac1, $3, $4    # encoding: [0x00,0x83,0x60,0xbc]

Modified: llvm/trunk/test/MC/Mips/micromips-dspr2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-dspr2/valid.s?rev=250685&r1=250684&r2=250685&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-dspr2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-dspr2/valid.s Mon Oct 19 02:16:26 2015
@@ -1,6 +1,14 @@
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
 
   .set noat
+  addqh.ph $3, $4, $5          # CHECK: addqh.ph $3, $4, $5     # encoding: [0x00,0xa4,0x18,0x4d]
+  addqh_r.ph $3, $4, $5        # CHECK: addqh_r.ph $3, $4, $5   # encoding: [0x00,0xa4,0x1c,0x4d]
+  addqh.w $3, $4, $5           # CHECK: addqh.w $3, $4, $5      # encoding: [0x00,0xa4,0x18,0x8d]
+  addqh_r.w $3, $4, $5         # CHECK: addqh_r.w $3, $4, $5    # encoding: [0x00,0xa4,0x1c,0x8d]
+  addu.ph $3, $4, $5           # CHECK: addu.ph $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x0d]
+  addu_s.ph $3, $4, $5         # CHECK: addu_s.ph $3, $4, $5    # encoding: [0x00,0xa4,0x1d,0x0d]
+  adduh.qb $3, $4, $5          # CHECK: adduh.qb $3, $4, $5     # encoding: [0x00,0xa4,0x19,0x4d]
+  adduh_r.qb $3, $4, $5        # CHECK: adduh_r.qb $3, $4, $5   # encoding: [0x00,0xa4,0x1d,0x4d]
   absq_s.qb $3, $4             # CHECK: absq_s.qb $3, $4           # encoding: [0x00,0x64,0x01,0x3c]
   dpa.w.ph $ac0, $3, $2        # CHECK: dpa.w.ph $ac0, $3, $2      # encoding: [0x00,0x43,0x00,0xbc]
   dpaqx_s.w.ph $ac3, $12, $7   # CHECK: dpaqx_s.w.ph $ac3, $12, $7 # encoding: [0x00,0xec,0xe2,0xbc]




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