[PATCH] D13740: Catch combine opportunities for redundant imuls

[Simon Pilgrim via llvm-commits]

RKSimon added a subscriber: RKSimon.

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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2221
@@ -2211,3 +2220,3 @@
     // Splat the sign bit into the register
     SDValue SGN =
         DAG.getNode(ISD::SRA, DL, VT, N0,
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zansari wrote:
> Will this replace both isConstantSplatVector and isa<Constan...> ? Or just the latter? I had a hard time trying to figure out the differences between the former, and isConstOrConstSplay to see if they can be both replaced.
You should be able to replace both with isConstOrConstSplat calls. In fact I think you could use isConstantIntBuildVectorOrConstantInt instead and match all constants not just those with a splatted value. This would definitely need a vector test case though.


http://reviews.llvm.org/D13740