[PATCH] D13656: [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.

Daniel Sanders via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 15 08:19:18 PDT 2015 

I haven't changed anything on that side of things, clang was already using it as an ASE. The
-mips16/-mno-mips16 options are still using -target-feature to pass the mips16 feature bit
to the backend and the mixed mode support is still being done via function attributes. I
also checked our internal buildbot was using -mips16 rather than -mcpu=mips16 before
committing.

> -----Original Message-----
> From: Reed Kotler
> Sent: 15 October 2015 16:03
> To: reviews+D13656+public+0afdc2a62da8828a at reviews.llvm.org; Daniel
> Sanders; Vasileios Kalintiris
> Cc: llvm-commits at lists.llvm.org
> Subject: RE: [PATCH] D13656: [mips][mips16] MIPS16 is not a
> CPU/Architecture but is an ASE.
> 
> DId you verify that there are no issues with mixed mips32/16 compilation?
> 
> There are test cases for that so it should still all be working but I was just
> checking how making it an ASE
> might change that.
> 
> 
> ________________________________________
> From: Daniel Sanders
> Sent: Thursday, October 15, 2015 7:36 AM
> To: Daniel Sanders; Vasileios Kalintiris
> Cc: Reed Kotler; llvm-commits at lists.llvm.org
> Subject: Re: [PATCH] D13656: [mips][mips16] MIPS16 is not a
> CPU/Architecture but is an ASE.
> 
> This revision was automatically updated to reflect the committed changes.
> Closed by commit rL250407: [mips][mips16] MIPS16 is not a CPU/Architecture
> but is an ASE. (authored by dsanders).
> 
> Changed prior to commit:
>   http://reviews.llvm.org/D13656?vs=37118&id=37482#toc
> 
> Repository:
>   rL LLVM
> 
> http://reviews.llvm.org/D13656
> 
> Files:
>   llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
>   llvm/trunk/lib/Target/Mips/Mips.td
>   llvm/trunk/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-
> after-call-entry.mir
>   llvm/trunk/test/CodeGen/MIR/Mips/memory-operands.mir
>   llvm/trunk/test/CodeGen/Mips/addi.ll
>   llvm/trunk/test/CodeGen/Mips/adjust-callstack-sp.ll
>   llvm/trunk/test/CodeGen/Mips/align16.ll
>   llvm/trunk/test/CodeGen/Mips/alloca16.ll
>   llvm/trunk/test/CodeGen/Mips/and1.ll
>   llvm/trunk/test/CodeGen/Mips/atomicops.ll
>   llvm/trunk/test/CodeGen/Mips/beqzc.ll
>   llvm/trunk/test/CodeGen/Mips/beqzc1.ll
>   llvm/trunk/test/CodeGen/Mips/br-jmp.ll
>   llvm/trunk/test/CodeGen/Mips/brconeq.ll
>   llvm/trunk/test/CodeGen/Mips/brconeqk.ll
>   llvm/trunk/test/CodeGen/Mips/brconeqz.ll
>   llvm/trunk/test/CodeGen/Mips/brconge.ll
>   llvm/trunk/test/CodeGen/Mips/brcongt.ll
>   llvm/trunk/test/CodeGen/Mips/brconle.ll
>   llvm/trunk/test/CodeGen/Mips/brconlt.ll
>   llvm/trunk/test/CodeGen/Mips/brconne.ll
>   llvm/trunk/test/CodeGen/Mips/brconnek.ll
>   llvm/trunk/test/CodeGen/Mips/brconnez.ll
>   llvm/trunk/test/CodeGen/Mips/brind.ll
>   llvm/trunk/test/CodeGen/Mips/brsize3.ll
>   llvm/trunk/test/CodeGen/Mips/brsize3a.ll
>   llvm/trunk/test/CodeGen/Mips/ci2.ll
>   llvm/trunk/test/CodeGen/Mips/cmplarge.ll
>   llvm/trunk/test/CodeGen/Mips/const1.ll
>   llvm/trunk/test/CodeGen/Mips/const4a.ll
>   llvm/trunk/test/CodeGen/Mips/const6.ll
>   llvm/trunk/test/CodeGen/Mips/const6a.ll
>   llvm/trunk/test/CodeGen/Mips/div.ll
>   llvm/trunk/test/CodeGen/Mips/div_rem.ll
>   llvm/trunk/test/CodeGen/Mips/divu.ll
>   llvm/trunk/test/CodeGen/Mips/divu_remu.ll
>   llvm/trunk/test/CodeGen/Mips/ex2.ll
>   llvm/trunk/test/CodeGen/Mips/extins.ll
>   llvm/trunk/test/CodeGen/Mips/f16abs.ll
>   llvm/trunk/test/CodeGen/Mips/fixdfsf.ll
>   llvm/trunk/test/CodeGen/Mips/fp16instrinsmc.ll
>   llvm/trunk/test/CodeGen/Mips/fp16mix.ll
>   llvm/trunk/test/CodeGen/Mips/fp16static.ll
>   llvm/trunk/test/CodeGen/Mips/helloworld.ll
>   llvm/trunk/test/CodeGen/Mips/hf16_1.ll
>   llvm/trunk/test/CodeGen/Mips/hf16call32.ll
>   llvm/trunk/test/CodeGen/Mips/hf16call32_body.ll
>   llvm/trunk/test/CodeGen/Mips/hf1_body.ll
>   llvm/trunk/test/CodeGen/Mips/hfptrcall.ll
>   llvm/trunk/test/CodeGen/Mips/i32k.ll
>   llvm/trunk/test/CodeGen/Mips/insn-zero-size-bb.ll
>   llvm/trunk/test/CodeGen/Mips/jtstat.ll
>   llvm/trunk/test/CodeGen/Mips/l3mc.ll
>   llvm/trunk/test/CodeGen/Mips/lb1.ll
>   llvm/trunk/test/CodeGen/Mips/lbu1.ll
>   llvm/trunk/test/CodeGen/Mips/lcb2.ll
>   llvm/trunk/test/CodeGen/Mips/lcb3c.ll
>   llvm/trunk/test/CodeGen/Mips/lcb4a.ll
>   llvm/trunk/test/CodeGen/Mips/lcb5.ll
>   llvm/trunk/test/CodeGen/Mips/lh1.ll
>   llvm/trunk/test/CodeGen/Mips/lhu1.ll
>   llvm/trunk/test/CodeGen/Mips/llcarry.ll
>   llvm/trunk/test/CodeGen/Mips/madd-msub.ll
>   llvm/trunk/test/CodeGen/Mips/mbrsize4a.ll
>   llvm/trunk/test/CodeGen/Mips/mips16-hf-attr-2.ll
>   llvm/trunk/test/CodeGen/Mips/mips16-hf-attr.ll
>   llvm/trunk/test/CodeGen/Mips/mips16_32_1.ll
>   llvm/trunk/test/CodeGen/Mips/mips16_32_10.ll
>   llvm/trunk/test/CodeGen/Mips/mips16_32_3.ll
>   llvm/trunk/test/CodeGen/Mips/mips16_32_4.ll
>   llvm/trunk/test/CodeGen/Mips/mips16_32_5.ll
>   llvm/trunk/test/CodeGen/Mips/mips16_32_6.ll
>   llvm/trunk/test/CodeGen/Mips/mips16_32_7.ll
>   llvm/trunk/test/CodeGen/Mips/mips16_fpret.ll
>   llvm/trunk/test/CodeGen/Mips/mips16ex.ll
>   llvm/trunk/test/CodeGen/Mips/mips16fpe.ll
>   llvm/trunk/test/CodeGen/Mips/misha.ll
>   llvm/trunk/test/CodeGen/Mips/mul.ll
>   llvm/trunk/test/CodeGen/Mips/mulll.ll
>   llvm/trunk/test/CodeGen/Mips/mulull.ll
>   llvm/trunk/test/CodeGen/Mips/neg1.ll
>   llvm/trunk/test/CodeGen/Mips/nomips16.ll
>   llvm/trunk/test/CodeGen/Mips/not1.ll
>   llvm/trunk/test/CodeGen/Mips/null.ll
>   llvm/trunk/test/CodeGen/Mips/or1.ll
>   llvm/trunk/test/CodeGen/Mips/powif64_16.ll
>   llvm/trunk/test/CodeGen/Mips/rem.ll
>   llvm/trunk/test/CodeGen/Mips/remu.ll
>   llvm/trunk/test/CodeGen/Mips/s2rem.ll
>   llvm/trunk/test/CodeGen/Mips/sb1.ll
>   llvm/trunk/test/CodeGen/Mips/sel1c.ll
>   llvm/trunk/test/CodeGen/Mips/sel2c.ll
>   llvm/trunk/test/CodeGen/Mips/selTBteqzCmpi.ll
>   llvm/trunk/test/CodeGen/Mips/selTBtnezCmpi.ll
>   llvm/trunk/test/CodeGen/Mips/selTBtnezSlti.ll
>   llvm/trunk/test/CodeGen/Mips/seleq.ll
>   llvm/trunk/test/CodeGen/Mips/seleqk.ll
>   llvm/trunk/test/CodeGen/Mips/selgek.ll
>   llvm/trunk/test/CodeGen/Mips/selgt.ll
>   llvm/trunk/test/CodeGen/Mips/selle.ll
>   llvm/trunk/test/CodeGen/Mips/selltk.ll
>   llvm/trunk/test/CodeGen/Mips/selne.ll
>   llvm/trunk/test/CodeGen/Mips/selnek.ll
>   llvm/trunk/test/CodeGen/Mips/selpat.ll
>   llvm/trunk/test/CodeGen/Mips/seteq.ll
>   llvm/trunk/test/CodeGen/Mips/seteqz.ll
>   llvm/trunk/test/CodeGen/Mips/setge.ll
>   llvm/trunk/test/CodeGen/Mips/setgek.ll
>   llvm/trunk/test/CodeGen/Mips/setle.ll
>   llvm/trunk/test/CodeGen/Mips/setlt.ll
>   llvm/trunk/test/CodeGen/Mips/setltk.ll
>   llvm/trunk/test/CodeGen/Mips/setne.ll
>   llvm/trunk/test/CodeGen/Mips/setuge.ll
>   llvm/trunk/test/CodeGen/Mips/setugt.ll
>   llvm/trunk/test/CodeGen/Mips/setule.ll
>   llvm/trunk/test/CodeGen/Mips/setult.ll
>   llvm/trunk/test/CodeGen/Mips/setultk.ll
>   llvm/trunk/test/CodeGen/Mips/sh1.ll
>   llvm/trunk/test/CodeGen/Mips/simplebr.ll
>   llvm/trunk/test/CodeGen/Mips/sll1.ll
>   llvm/trunk/test/CodeGen/Mips/sll2.ll
>   llvm/trunk/test/CodeGen/Mips/sr1.ll
>   llvm/trunk/test/CodeGen/Mips/sra1.ll
>   llvm/trunk/test/CodeGen/Mips/sra2.ll
>   llvm/trunk/test/CodeGen/Mips/srl1.ll
>   llvm/trunk/test/CodeGen/Mips/srl2.ll
>   llvm/trunk/test/CodeGen/Mips/stchar.ll
>   llvm/trunk/test/CodeGen/Mips/stldst.ll
>   llvm/trunk/test/CodeGen/Mips/sub1.ll
>   llvm/trunk/test/CodeGen/Mips/sub2.ll
>   llvm/trunk/test/CodeGen/Mips/tail16.ll
>   llvm/trunk/test/CodeGen/Mips/tailcall.ll
>   llvm/trunk/test/CodeGen/Mips/tls16.ll
>   llvm/trunk/test/CodeGen/Mips/tls16_2.ll
>   llvm/trunk/test/CodeGen/Mips/trap1.ll
>   llvm/trunk/test/CodeGen/Mips/ul1.ll
>   llvm/trunk/test/CodeGen/Mips/xor1.ll

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