[llvm] r250377 - [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions
Hrvoje Varga via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 15 00:23:06 PDT 2015
Author: hvarga
Date: Thu Oct 15 02:23:06 2015
New Revision: 250377
URL: http://llvm.org/viewvc/llvm-project?rev=250377&view=rev
Log:
[mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions
Differential Revision: http://reviews.llvm.org/D11631
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
llvm/trunk/test/MC/Mips/micromips-control-instructions.s
llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td?rev=250377&r1=250376&r2=250377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td Thu Oct 15 02:23:06 2015
@@ -418,6 +418,22 @@ class LWL_FM_MM<bits<4> funct> {
let Inst{11-0} = addr{11-0};
}
+class POOL32C_STEVA_LDEVA_FM_MM<bits<4> type, bits<3> funct> {
+ bits<5> rt;
+ bits<21> addr;
+ bits<5> base = addr{20-16};
+ bits<9> offset = addr{8-0};
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0x18;
+ let Inst{25-21} = rt;
+ let Inst{20-16} = base;
+ let Inst{15-12} = type;
+ let Inst{11-9} = funct;
+ let Inst{8-0} = offset;
+}
+
class CMov_F_I_FM_MM<bits<7> func> : MMArch {
bits<5> rd;
bits<5> rs;
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=250377&r1=250376&r2=250377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Thu Oct 15 02:23:06 2015
@@ -751,6 +751,16 @@ let DecoderNamespace = "MicroMips", Pred
LWL_FM_MM<0x8>;
def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x9>;
+ let DecoderMethod = "DecodeMemMMImm9" in {
+ def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_12>,
+ POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
+ def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_12>,
+ POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
+ def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_12>,
+ POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
+ def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_12>,
+ POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
+ }
/// Load and Store Instructions - multiple
def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt?rev=250377&r1=250376&r2=250377&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt Thu Oct 15 02:23:06 2015
@@ -183,3 +183,7 @@
0xa4 0x60 0x08 0xa8 # CHECK: sbe $5, 8($4)
0xa4 0x60 0x08 0xaa # CHECK: she $5, 8($4)
0xa4 0x60 0x08 0xae # CHECK: swe $5, 8($4)
+0x03 0x63 0x05 0xa2 # CHECK: swre $24, 5($3)
+0x03 0x63 0x05 0xa0 # CHECK: swle $24, 5($3)
+0x03 0x63 0x05 0x66 # CHECK: lwre $24, 5($3)
+0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4)
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt?rev=250377&r1=250376&r2=250377&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt Thu Oct 15 02:23:06 2015
@@ -183,3 +183,7 @@
0x60 0xa4 0xa8 0x08 # CHECK: sbe $5, 8($4)
0x60 0xa4 0xaa 0x08 # CHECK: she $5, 8($4)
0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4)
+0x63 0x03 0xa2 0x05 # CHECK: swre $24, 5($3)
+0x63 0x03 0xa0 0x05 # CHECK: swle $24, 5($3)
+0x63 0x03 0x66 0x05 # CHECK: lwre $24, 5($3)
+0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4)
Modified: llvm/trunk/test/MC/Mips/micromips-control-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-control-instructions.s?rev=250377&r1=250376&r2=250377&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-control-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-control-instructions.s Thu Oct 15 02:23:06 2015
@@ -42,6 +42,10 @@
# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4]
# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
# CHECK-EL: prefx 1, $3($5) # encoding: [0x65,0x54,0xa0,0x09]
+# CHECK-EL: swre $24, 5($3) # encoding: [0x03,0x63,0x05,0xa2]
+# CHECK-EL: swle $24, 5($3) # encoding: [0x03,0x63,0x05,0xa0]
+# CHECK-EL: lwre $24, 5($3) # encoding: [0x03,0x63,0x05,0x66]
+# CHECK-EL: lwle $24, 2($4) # encoding: [0x04,0x63,0x02,0x64]
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
@@ -78,6 +82,10 @@
# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
# CHECK-EB: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0]
+# CHECK-EB: swre $24, 5($3) # encoding: [0x63,0x03,0xa2,0x05]
+# CHECK-EB: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05]
+# CHECK-EB: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05]
+# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02]
sdbbp
sdbbp 34
@@ -109,3 +117,7 @@
prefe 1, 8($5)
cachee 1, 8($5)
prefx 1, $3($5)
+ swre $24, 5($3)
+ swle $24, 5($3)
+ lwre $24, 5($3)
+ lwle $24, 2($4)
Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s?rev=250377&r1=250376&r2=250377&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s Thu Oct 15 02:23:06 2015
@@ -14,4 +14,5 @@
lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ swre $24, 5($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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