[PATCH] D12007: [AMDGPU] Use the general SMAX/SMIN/UMAX/UMIN pattern matching and remove the AMDGPU implementation

[Matt Arsenault via llvm-commits]

On 08/13/2015 02:40 PM, Simon Pilgrim wrote:
> This revision was automatically updated to reflect the committed changes.
> Closed by commit rL244960: [AMDGPU] Use the general SMAX/SMIN/UMAX/UMIN pattern matching and remove the… (authored by RKSimon).
>
> Changed prior to commit:
>    http://reviews.llvm.org/D12007?vs=32043&id=32096#toc
>
> Repository:
>    rL LLVM
>
> http://reviews.llvm.org/D12007
>
> Files:
>    llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
>    llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h
>
> Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
> ===================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
> @@ -1167,45 +1167,6 @@
>     return SDValue();
>   }
>   
> -// FIXME: Remove this when combines added to DAGCombiner.
> -SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
> -                                             EVT VT,
> -                                             SDValue LHS,
> -                                             SDValue RHS,
> -                                             SDValue True,
> -                                             SDValue False,
> -                                             SDValue CC,
> -                                             SelectionDAG &DAG) const {
> -  if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
> -    return SDValue();
> -
> -  ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
> -  switch (CCOpcode) {
> -  case ISD::SETULE:
> -  case ISD::SETULT: {
> -    unsigned Opc = (LHS == True) ? ISD::UMIN : ISD::UMAX;
> -    return DAG.getNode(Opc, DL, VT, LHS, RHS);
> -  }
> -  case ISD::SETLE:
> -  case ISD::SETLT: {
> -    unsigned Opc = (LHS == True) ? ISD::SMIN : ISD::SMAX;
> -    return DAG.getNode(Opc, DL, VT, LHS, RHS);
> -  }
> -  case ISD::SETGT:
> -  case ISD::SETGE: {
> -    unsigned Opc = (LHS == True) ? ISD::SMAX : ISD::SMIN;
> -    return DAG.getNode(Opc, DL, VT, LHS, RHS);
> -  }
> -  case ISD::SETUGE:
> -  case ISD::SETUGT: {
> -    unsigned Opc = (LHS == True) ? ISD::UMAX : ISD::UMIN;
> -    return DAG.getNode(Opc, DL, VT, LHS, RHS);
> -  }
> -  default:
> -    return SDValue();
> -  }
> -}
> -
>   SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
>                                                     SelectionDAG &DAG) const {
>     LoadSDNode *Load = cast<LoadSDNode>(Op);
> @@ -2511,12 +2472,6 @@
>   
>         if (VT == MVT::f32)
>           return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
> -
> -      // TODO: Implement min / max Evergreen instructions.
> -      if (VT == MVT::i32 &&
> -          Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
> -        return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
> -      }
>       }
>   
>       break;
> Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h
> ===================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h
> @@ -165,14 +165,6 @@
>                                  SDValue False,
>                                  SDValue CC,
>                                  DAGCombinerInfo &DCI) const;
> -  SDValue CombineIMinMax(SDLoc DL,
> -                         EVT VT,
> -                         SDValue LHS,
> -                         SDValue RHS,
> -                         SDValue True,
> -                         SDValue False,
> -                         SDValue CC,
> -                         SelectionDAG &DAG) const;
>   
>     const char* getTargetNodeName(unsigned Opcode) const override;
>   
>
>
I think we should resurrect this combine and move it to DAGCombiner. 
Since this patch min/max on the components of scalarized vectors isn't 
matched