[PATCH] Marked Swift Machine Scheduler Model as incomplete

[Andrew Trick via llvm-commits]

> On Oct 9, 2015, at 11:30 AM, Matthias Braun <matze at braunis.de> wrote:
> 
> Shouldn't we change tablegen to abort if CompleteModel == 1 and not all instructions are covered or is there a reason why such a check can't work reliably? I'd be happy to put that on my TODO list.

I’m not really opposed to that, but some instructions are deliberately unsupported on some machines. The current way of dealing with that is to assert at compile time.

Andy

> 
> - Matthias
> 
>> On Oct 9, 2015, at 11:22 AM, Andrew Trick <atrick at apple.com> wrote:
>> 
>> Hi Christof,
>> 
>> The change is fine with me as long as you file a bug to get those instructions added to the model.
>> 
>> Andy
>> 
>>> On Oct 9, 2015, at 8:53 AM, Christof Douma <Christof.Douma at arm.com> wrote:
>>> 
>>> Hi.
>>> 
>>> I've got a 1-line change to the SwiftModel to mark the model as incomplete.
>>> Can I get a review on this?
>>> 
>>> Thanks,
>>> Christof
>>> ------------
>>> Marked Swift Machine Scheduler Model as incomplete
>>> 
>>> Swift Machine Scheduler Model is incomplete. There are instructions
>>> missing which can trigger the "incomplete machine model" abort. This was
>>> observed when a downstream SchedMachineModel was added to the ARM
>>> target.
>>> 
>>> Change-Id: Ie43cbc8d529b6a1257a5d7b1e69e6f40d504b842
>>> ---
>>> lib/Target/ARM/ARMScheduleSwift.td | 1 +
>>> 1 file changed, 1 insertion(+)
>>> 
>>> diff --git a/lib/Target/ARM/ARMScheduleSwift.td
>>> b/lib/Target/ARM/ARMScheduleSwift.td
>>> index 6f5740f..64b477d 100644
>>> --- a/lib/Target/ARM/ARMScheduleSwift.td
>>> +++ b/lib/Target/ARM/ARMScheduleSwift.td
>>> @@ -43,6 +43,7 @@ def SwiftModel : SchedMachineModel {
>>> let MicroOpBufferSize = 45; // Based on NEON renamed registers.
>>> let LoadLatency = 3;
>>> let MispredictPenalty = 14; // A branch direction mispredict.
>>> +  let CompleteModel = 0;    // FIXME: Remove if all instructions are
>>> covered.
>>> }
>>> 
>>> // Swift predicates.
>>> -- 
>>> 1.8.3
>>> 
>>> 
>> 
>