[PATCH] D13121: Improve ISel across lane float min/max reduction

[Jun Bum Lim via llvm-commits]

junbuml added a comment.

Just final minor changes. 
I will commit this tomorrow unless I get any comment for this minor changes.


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8684
@@ -8676,3 +8683,3 @@
   case ISD::ADD:
     Opcode = AArch64ISD::UADDV;
     break;
----------------
Use intrinsic for F[MAX|MIN]NMV, but use SDNode for addv and  [s|u][min|max]v.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8866
@@ -8833,1 +8865,3 @@
 
+  if (VTy.getSizeInBits() < 64)
+    return SDValue();
----------------
Add check for minimum size in case of the input vector is too small.


http://reviews.llvm.org/D13121