[PATCH] D13527: AMDGPU: Exclude SGPRs except m0 from movrel operands

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm.

Due to the constant bus restriction a literal constant
or SGPR other than m0 can't be used depite the operand
encoding. Fix the operand class to avoid having to manually
legalize the constant bus restriction.
    
The test change is a surprising scheduling change which
I'm not really sure why it happened since none of these
instructions are used in it. I'm guessing one of the generated
getCommon*Class functions now behaves somewhat differently.
This could probably be avoided by not allowing m0 either,
since that is probably not really useful.

http://reviews.llvm.org/D13527

Files:
  lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  lib/Target/AMDGPU/SIInstrInfo.td
  lib/Target/AMDGPU/SIInstructions.td
  lib/Target/AMDGPU/SIRegisterInfo.td
  test/CodeGen/AMDGPU/ds_read2st64.ll
  test/MC/AMDGPU/vop1-err.s
  test/MC/AMDGPU/vop1.s

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