[PATCH] D13442: [AArch64] Fold vector fmul/fdiv by pow2 into floating-point/fixed-point conversions.

[Tim Northover via llvm-commits]

t.p.northover added a comment.

Thanks for updating the patch, Chad. Still got a few more issues...


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7538
@@ +7537,3 @@
+// elements are the same constant, C, and Log2(C) ranges from 1 to Range.
+static bool isConstVecPow2(SDValue ConstVec, bool IsSigned, uint64_t &C,
+                           unsigned Range) {
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I've just noticed this started life in ARMISelLowering.cpp; since we're improving it here, can we fix that one too? Or even share the implementation somewhere (BuildVectorSDNode, or perhaps SelectionDAG if you anticipate handling more cases in the future)

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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7543
@@ +7542,3 @@
+    ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
+    if (!CN || !UndefElements.none())
+      return false;
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Why are we bailing on undef here?

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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7549
@@ +7548,3 @@
+    APFloat APF = CN->getValueAPF();
+    if (APF.convertToInteger(&C0, 64, IsSigned, APFloat::rmTowardZero, &IsExact) != APFloat::opOK || !IsExact)
+      return false;
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I don't think this can handle 2^64. Really, we might as well convert to an APSInt and use exactLogBase2 or something.


http://reviews.llvm.org/D13442