[PATCH] D12985: [ARM] Take into account address spaces in interleaved access vectorization

[Jeroen Ketema via llvm-commits]

jketema created this revision.
jketema added reviewers: sbaranga, rengolin.
jketema added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

The vector being loaded might not be in address space 0. In this case the vldn/vstn call creation will trigger an assert in CallInst:Create, because the argument type and the parameter are in different address spaces. Resolve this by adding an appropriate address space cast.

http://reviews.llvm.org/D12985

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  test/CodeGen/ARM/arm-interleaved-accesses.ll

Index: test/CodeGen/ARM/arm-interleaved-accesses.ll
===================================================================
--- test/CodeGen/ARM/arm-interleaved-accesses.ll
+++ test/CodeGen/ARM/arm-interleaved-accesses.ll
@@ -202,3 +202,24 @@
   store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4
   ret void
 }
+
+; The following test cases check that address spaces are properly handled
+
+; CHECK-LABEL: load_address_space
+; CHECK: vld3.32
+define void @load_address_space(<4 x i32> addrspace(1)* %A, <2 x i32>* %B) {
+ %tmp = load <4 x i32>, <4 x i32> addrspace(1)* %A
+ %interleaved = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 0, i32 3>
+ store <2 x i32> %interleaved, <2 x i32>* %B
+ ret void
+}
+
+; CHECK-LABEL: store_address_space
+; CHECK: vst2.32
+define void @store_address_space(<2 x i32>* %A, <2 x i32>* %B, <4 x i32> addrspace(1)* %C) {
+ %tmp0 = load <2 x i32>, <2 x i32>* %A
+ %tmp1 = load <2 x i32>, <2 x i32>* %B
+ %interleaved = shufflevector <2 x i32> %tmp0, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+ store <4 x i32> %interleaved, <4 x i32> addrspace(1)* %C
+ ret void
+}
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -11703,8 +11703,10 @@
   IRBuilder<> Builder(LI);
   SmallVector<Value *, 2> Ops;
 
-  Type *Int8Ptr = Builder.getInt8PtrTy(LI->getPointerAddressSpace());
-  Ops.push_back(Builder.CreateBitCast(LI->getPointerOperand(), Int8Ptr));
+  Type *Int8PtrAddr = Builder.getInt8PtrTy(LI->getPointerAddressSpace());
+  Type *Int8Ptr = Builder.getInt8PtrTy();
+  Ops.push_back(Builder.CreateAddrSpaceCast(
+      Builder.CreateBitCast(LI->getPointerOperand(), Int8PtrAddr), Int8Ptr));
   Ops.push_back(Builder.getInt32(LI->getAlignment()));
 
   CallInst *VldN = Builder.CreateCall(VldnFunc, Ops, "vldN");
@@ -11803,8 +11805,10 @@
 
   SmallVector<Value *, 6> Ops;
 
-  Type *Int8Ptr = Builder.getInt8PtrTy(SI->getPointerAddressSpace());
-  Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), Int8Ptr));
+  Type *Int8PtrAddr = Builder.getInt8PtrTy(SI->getPointerAddressSpace());
+  Type *Int8Ptr = Builder.getInt8PtrTy();
+  Ops.push_back(Builder.CreateAddrSpaceCast(
+    Builder.CreateBitCast(SI->getPointerOperand(), Int8PtrAddr), Int8Ptr));
 
   // Split the shufflevector operands into sub vectors for the new vstN call.
   for (unsigned i = 0; i < Factor; i++)


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