[llvm] r247880 - [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions
Zoran Jovanovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 17 03:14:10 PDT 2015
Author: zjovanovic
Date: Thu Sep 17 05:14:09 2015
New Revision: 247880
URL: http://llvm.org/viewvc/llvm-project?rev=247880&view=rev
Log:
[mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions
Differential Revision: http://reviews.llvm.org/D9658
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
llvm/trunk/test/MC/Mips/micromips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=247880&r1=247879&r2=247880&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Thu Sep 17 05:14:09 2015
@@ -1736,6 +1736,12 @@ bool MipsAsmParser::processInstruction(M
if (Imm < -1 || Imm > 14)
return Error(IDLoc, "immediate operand value out of range");
break;
+ case Mips::TEQ_MM:
+ case Mips::TGE_MM:
+ case Mips::TGEU_MM:
+ case Mips::TLT_MM:
+ case Mips::TLTU_MM:
+ case Mips::TNE_MM:
case Mips::SB16_MM:
Opnd = Inst.getOperand(2);
if (!Opnd.isImm())
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=247880&r1=247879&r2=247880&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Thu Sep 17 05:14:09 2015
@@ -974,4 +974,16 @@ def B_MM_Pseudo : UncondBranchMMPseudo<"
let Predicates = [InMicroMips] in {
def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
+def : MipsInstAlias<"teq $rs, $rt",
+ (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def : MipsInstAlias<"tge $rs, $rt",
+ (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def : MipsInstAlias<"tgeu $rs, $rt",
+ (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def : MipsInstAlias<"tlt $rs, $rt",
+ (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def : MipsInstAlias<"tltu $rs, $rt",
+ (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def : MipsInstAlias<"tne $rs, $rt",
+ (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=247880&r1=247879&r2=247880&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Sep 17 05:14:09 2015
@@ -1314,12 +1314,14 @@ let DecoderNamespace = "COP3_" in {
def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
-def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
-def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
-def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
-def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
-def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
-def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
+ def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
+ def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
+ def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
+ def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
+ def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
+}
def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
ISA_MIPS2_NOT_32R6_64R6;
@@ -1695,20 +1697,20 @@ let AdditionalPredicates = [NotInMicroMi
def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
}
def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
-
-def : MipsInstAlias<"teq $rs, $rt",
- (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
-def : MipsInstAlias<"tge $rs, $rt",
- (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
-def : MipsInstAlias<"tgeu $rs, $rt",
- (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
-def : MipsInstAlias<"tlt $rs, $rt",
- (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
-def : MipsInstAlias<"tltu $rs, $rt",
- (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
-def : MipsInstAlias<"tne $rs, $rt",
- (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
-
+let AdditionalPredicates = [NotInMicroMips] in {
+ def : MipsInstAlias<"teq $rs, $rt",
+ (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+ def : MipsInstAlias<"tge $rs, $rt",
+ (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+ def : MipsInstAlias<"tgeu $rs, $rt",
+ (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+ def : MipsInstAlias<"tlt $rs, $rt",
+ (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+ def : MipsInstAlias<"tltu $rs, $rt",
+ (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+ def : MipsInstAlias<"tne $rs, $rt",
+ (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+}
def : MipsInstAlias<"sll $rd, $rt, $rs",
(SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sub, $rd, $rs, $imm",
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips.txt?rev=247880&r1=247879&r2=247880&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips.txt Thu Sep 17 05:14:09 2015
@@ -187,17 +187,17 @@
0x40 0x06 0x02 0x9a # CHECK: bltz $6, 1332
-0x01 0x28 0x00 0x3c # CHECK: teq $8, $9, 0
+0x01 0x28 0x00 0x3c # CHECK: teq $8, $9
-0x01 0x28 0x02 0x3c # CHECK: tge $8, $9, 0
+0x01 0x28 0x02 0x3c # CHECK: tge $8, $9
-0x01 0x28 0x04 0x3c # CHECK: tgeu $8, $9, 0
+0x01 0x28 0x04 0x3c # CHECK: tgeu $8, $9
-0x01 0x28 0x08 0x3c # CHECK: tlt $8, $9, 0
+0x01 0x28 0x08 0x3c # CHECK: tlt $8, $9
-0x01 0x28 0x0a 0x3c # CHECK: tltu $8, $9, 0
+0x01 0x28 0x0a 0x3c # CHECK: tltu $8, $9
-0x01 0x28 0x0c 0x3c # CHECK: tne $8, $9, 0
+0x01 0x28 0x0c 0x3c # CHECK: tne $8, $9
0x41,0xc9,0x45,0x67 # CHECK: teqi $9, 17767
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt?rev=247880&r1=247879&r2=247880&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt Thu Sep 17 05:14:09 2015
@@ -355,3 +355,27 @@
0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5)
0x60 0x25 0xa4 0x08 # CHECK: prefe 1, 8($5)
+
+0x01 0x28 0x00 0x3c # CHECK: teq $8, $9
+
+0x00 0xe5 0xf0 0x3c # CHECK: teq $5, $7, 15
+
+0x01 0x47 0x02 0x3c # CHECK: tge $7, $10
+
+0x02 0x67 0xf2 0x3c # CHECK: tge $7, $19, 15
+
+0x03 0x96 0x04 0x3c # CHECK: tgeu $22, $gp
+
+0x01 0xd4 0xf4 0x3c # CHECK: tgeu $20, $14, 15
+
+0x01 0xaf 0x08 0x3c # CHECK: tlt $15, $13
+
+0x02 0x62 0xf8 0x3c # CHECK: tlt $2, $19, 15
+
+0x02 0x0b 0x0a 0x3c # CHECK: tltu $11, $16
+
+0x03 0xb0 0xfa 0x3c # CHECK: tltu $16, $sp, 15
+
+0x02 0x26 0x0c 0x3c # CHECK: tne $6, $17
+
+0x01 0x07 0xfc 0x3c # CHECK: tne $7, $8, 15
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt?rev=247880&r1=247879&r2=247880&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt Thu Sep 17 05:14:09 2015
@@ -225,3 +225,27 @@
0x09 0x94 # CHECK: lbu16 $3, 4($17)
0x09 0x9f # CHECK: lbu16 $3, -1($17)
+
+0x01 0x28 0x00 0x3c # CHECK: teq $8, $9
+
+0x00 0xe5 0xf0 0x3c # CHECK: teq $5, $7, 15
+
+0x01 0x47 0x02 0x3c # CHECK: tge $7, $10
+
+0x02 0x67 0xf2 0x3c # CHECK: tge $7, $19, 15
+
+0x03 0x96 0x04 0x3c # CHECK: tgeu $22, $gp
+
+0x01 0xd4 0xf4 0x3c # CHECK: tgeu $20, $14, 15
+
+0x01 0xaf 0x08 0x3c # CHECK: tlt $15, $13
+
+0x02 0x62 0xf8 0x3c # CHECK: tlt $2, $19, 15
+
+0x02 0x0b 0x0a 0x3c # CHECK: tltu $11, $16
+
+0x03 0xb0 0xfa 0x3c # CHECK: tltu $16, $sp, 15
+
+0x02 0x26 0x0c 0x3c # CHECK: tne $6, $17
+
+0x01 0x07 0xfc 0x3c # CHECK: tne $7, $8, 15
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt?rev=247880&r1=247879&r2=247880&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt Thu Sep 17 05:14:09 2015
@@ -187,17 +187,17 @@
0x06 0x40 0x9a 0x02 # CHECK: bltz $6, 1332
-0x28 0x01 0x3c 0x00 # CHECK: teq $8, $9, 0
+0x28 0x01 0x3c 0x00 # CHECK: teq $8, $9
-0x28 0x01 0x3c 0x02 # CHECK: tge $8, $9, 0
+0x28 0x01 0x3c 0x02 # CHECK: tge $8, $9
-0x28 0x01 0x3c 0x04 # CHECK: tgeu $8, $9, 0
+0x28 0x01 0x3c 0x04 # CHECK: tgeu $8, $9
-0x28 0x01 0x3c 0x08 # CHECK: tlt $8, $9, 0
+0x28 0x01 0x3c 0x08 # CHECK: tlt $8, $9
-0x28 0x01 0x3c 0x0a # CHECK: tltu $8, $9, 0
+0x28 0x01 0x3c 0x0a # CHECK: tltu $8, $9
-0x28 0x01 0x3c 0x0c # CHECK: tne $8, $9, 0
+0x28 0x01 0x3c 0x0c # CHECK: tne $8, $9
0xc9 0x41 0x67 0x45 # CHECK: teqi $9, 17767
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=247880&r1=247879&r2=247880&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Thu Sep 17 05:14:09 2015
@@ -32,3 +32,27 @@
lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
lw16 $17, 8($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ teq $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ tge $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tge $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tge $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ tgeu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tgeu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tgeu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tlt $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ tltu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tltu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tltu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ tne $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tne $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tne $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ teq $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tge $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tgeu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tltu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tne $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=247880&r1=247879&r2=247880&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Thu Sep 17 05:14:09 2015
@@ -181,4 +181,15 @@
srl16 $3, $6, 8 # CHECK: srl16 $3, $6, 8 # encoding: [0x25,0xe1]
prefe 1, 8($5) # CHECK: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
cachee 1, 8($5) # CHECK: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
-
+ teq $8, $9 # CHECK: teq $8, $9 # encoding: [0x01,0x28,0x00,0x3c]
+ teq $5, $7, 15 # CHECK: teq $5, $7, 15 # encoding: [0x00,0xe5,0xf0,0x3c]
+ tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x01,0x47,0x02,0x3c]
+ tge $7, $19, 15 # CHECK: tge $7, $19, 15 # encoding: [0x02,0x67,0xf2,0x3c]
+ tgeu $22, $gp # CHECK: tgeu $22, $gp # encoding: [0x03,0x96,0x04,0x3c]
+ tgeu $20, $14, 15 # CHECK: tgeu $20, $14, 15 # encoding: [0x01,0xd4,0xf4,0x3c]
+ tlt $15, $13 # CHECK: tlt $15, $13 # encoding: [0x01,0xaf,0x08,0x3c]
+ tlt $2, $19, 15 # CHECK: tlt $2, $19, 15 # encoding: [0x02,0x62,0xf8,0x3c]
+ tltu $11, $16 # CHECK: tltu $11, $16 # encoding: [0x02,0x0b,0x0a,0x3c]
+ tltu $16, $sp, 15 # CHECK: tltu $16, $sp, 15 # encoding: [0x03,0xb0,0xfa,0x3c]
+ tne $6, $17 # CHECK: tne $6, $17 # encoding: [0x02,0x26,0x0c,0x3c]
+ tne $7, $8, 15 # CHECK: tne $7, $8, 15 # encoding: [0x01,0x07,0xfc,0x3c]
Modified: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/invalid.s?rev=247880&r1=247879&r2=247880&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s Thu Sep 17 05:14:09 2015
@@ -38,3 +38,27 @@
dmodu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
dmodu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
dmodu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ teq $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ tge $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tge $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tge $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ tgeu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tgeu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tgeu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tlt $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ tltu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tltu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tltu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ tne $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tne $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tne $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+ teq $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tge $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tgeu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tltu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ tne $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=247880&r1=247879&r2=247880&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Thu Sep 17 05:14:09 2015
@@ -97,5 +97,17 @@ a:
cvt.s.d $f2, $f4 # CHECK: cvt.s.d $f2, $f4 # encoding: [0x54,0x44,0x1b,0x7b]
cvt.s.w $f3, $f4 # CHECK: cvt.s.w $f3, $f4 # encoding: [0x54,0x64,0x3b,0x7b]
cvt.s.l $f3, $f4 # CHECK: cvt.s.l $f3, $f4 # encoding: [0x54,0x64,0x5b,0x7b]
+ teq $8, $9 # CHECK: teq $8, $9 # encoding: [0x01,0x28,0x00,0x3c]
+ teq $5, $7, 15 # CHECK: teq $5, $7, 15 # encoding: [0x00,0xe5,0xf0,0x3c]
+ tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x01,0x47,0x02,0x3c]
+ tge $7, $19, 15 # CHECK: tge $7, $19, 15 # encoding: [0x02,0x67,0xf2,0x3c]
+ tgeu $22, $gp # CHECK: tgeu $22, $gp # encoding: [0x03,0x96,0x04,0x3c]
+ tgeu $20, $14, 15 # CHECK: tgeu $20, $14, 15 # encoding: [0x01,0xd4,0xf4,0x3c]
+ tlt $15, $13 # CHECK: tlt $15, $13 # encoding: [0x01,0xaf,0x08,0x3c]
+ tlt $2, $19, 15 # CHECK: tlt $2, $19, 15 # encoding: [0x02,0x62,0xf8,0x3c]
+ tltu $11, $16 # CHECK: tltu $11, $16 # encoding: [0x02,0x0b,0x0a,0x3c]
+ tltu $16, $sp, 15 # CHECK: tltu $16, $sp, 15 # encoding: [0x03,0xb0,0xfa,0x3c]
+ tne $6, $17 # CHECK: tne $6, $17 # encoding: [0x02,0x26,0x0c,0x3c]
+ tne $7, $8, 15 # CHECK: tne $7, $8, 15 # encoding: [0x01,0x07,0xfc,0x3c]
1:
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