[llvm] r247702 - Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.

Daniel Sanders via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 15 09:17:29 PDT 2015


Author: dsanders
Date: Tue Sep 15 11:17:27 2015
New Revision: 247702

URL: http://llvm.org/viewvc/llvm-project?rev=247702&view=rev
Log:
Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.

Eric has replied and has demanded the patch be reverted.


Removed:
    llvm/trunk/include/llvm/ADT/TargetTuple.h
    llvm/trunk/lib/Support/TargetTuple.cpp
Modified:
    llvm/trunk/include/llvm/MC/MCELFObjectWriter.h
    llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
    llvm/trunk/include/llvm/Support/TargetRegistry.h
    llvm/trunk/include/llvm/Target/TargetMachine.h
    llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
    llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
    llvm/trunk/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp
    llvm/trunk/lib/MC/MCDisassembler/MCRelocationInfo.cpp
    llvm/trunk/lib/MC/MCSubtargetInfo.cpp
    llvm/trunk/lib/Support/CMakeLists.txt
    llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
    llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
    llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
    llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
    llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
    llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
    llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
    llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
    llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
    llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
    llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
    llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h
    llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
    llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
    llvm/trunk/lib/Target/BPF/BPFSubtarget.cpp
    llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
    llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
    llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
    llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
    llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
    llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
    llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
    llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
    llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
    llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
    llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
    llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
    llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
    llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp
    llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
    llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
    llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h
    llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
    llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp
    llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
    llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
    llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
    llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h
    llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
    llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
    llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
    llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
    llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
    llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
    llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp
    llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h
    llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
    llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
    llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
    llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
    llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
    llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h
    llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
    llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
    llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
    llvm/trunk/lib/Target/TargetSubtargetInfo.cpp
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
    llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp
    llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h
    llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
    llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp
    llvm/trunk/tools/dsymutil/DwarfLinker.cpp
    llvm/trunk/tools/llvm-mc/llvm-mc.cpp
    llvm/trunk/tools/llvm-objdump/MachODump.cpp
    llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
    llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp
    llvm/trunk/utils/TableGen/SubtargetEmitter.cpp

Removed: llvm/trunk/include/llvm/ADT/TargetTuple.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/TargetTuple.h?rev=247701&view=auto
==============================================================================
--- llvm/trunk/include/llvm/ADT/TargetTuple.h (original)
+++ llvm/trunk/include/llvm/ADT/TargetTuple.h (removed)
@@ -1,431 +0,0 @@
-//===-- llvm/ADT/TargetTuple.h - Target tuple class -------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-/// @file
-/// This file contains the definitions for TargetTuples which describe the
-/// target in a unique unambiguous way. This is in contrast to the GNU triples
-/// handled by the Triple class which are more of a guideline than a
-/// description and whose meaning can be overridden by vendors and distributors.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_ADT_TARGETTUPLE_H
-#define LLVM_ADT_TARGETTUPLE_H
-
-#include "llvm/ADT/Twine.h"
-#include "llvm/ADT/Triple.h"
-
-// Some system headers or GCC predefined macros conflict with identifiers in
-// this file.  Undefine them here.
-#undef NetBSD
-#undef mips
-#undef sparc
-
-namespace llvm {
-
-/// TargetTuple is currently a proxy for Triple but will become an unambiguous,
-/// authoratitive, and mutable counterpart to the GNU triples handled by Triple.
-class TargetTuple {
-public:
-  // FIXME: Don't duplicate Triple::ArchType. It's worth mentioning that these
-  //        these values don't have to match Triple::ArchType. For example, it
-  //        would be fairly sensible to have a single 'mips' architecture and
-  //        distinguish endianness and ABI elsewhere.
-  enum ArchType {
-    UnknownArch,
-
-    arm,        // ARM (little endian): arm, armv.*, xscale
-    armeb,      // ARM (big endian): armeb
-    aarch64,    // AArch64 (little endian): aarch64
-    aarch64_be, // AArch64 (big endian): aarch64_be
-    bpfel,      // eBPF or extended BPF or 64-bit BPF (little endian)
-    bpfeb,      // eBPF or extended BPF or 64-bit BPF (big endian)
-    hexagon,    // Hexagon: hexagon
-    mips,       // MIPS: mips, mipsallegrex
-    mipsel,     // MIPSEL: mipsel, mipsallegrexel
-    mips64,     // MIPS64: mips64
-    mips64el,   // MIPS64EL: mips64el
-    msp430,     // MSP430: msp430
-    ppc,        // PPC: powerpc
-    ppc64,      // PPC64: powerpc64, ppu
-    ppc64le,    // PPC64LE: powerpc64le
-    r600,       // R600: AMD GPUs HD2XXX - HD6XXX
-    amdgcn,     // AMDGCN: AMD GCN GPUs
-    sparc,      // Sparc: sparc
-    sparcv9,    // Sparcv9: Sparcv9
-    sparcel,    // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
-    systemz,    // SystemZ: s390x
-    tce,        // TCE (http://tce.cs.tut.fi/): tce
-                // FIXME: thumb/thumbeb will be merged into arm/armeb soon.
-    thumb,      // Thumb (little endian): thumb, thumbv.*
-    thumbeb,    // Thumb (big endian): thumbeb
-    x86,        // X86: i[3-9]86
-    x86_64,     // X86-64: amd64, x86_64
-    xcore,      // XCore: xcore
-    nvptx,      // NVPTX: 32-bit
-    nvptx64,    // NVPTX: 64-bit
-    le32,       // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)
-    le64,       // le64: generic little-endian 64-bit CPU (PNaCl / Emscripten)
-    amdil,      // AMDIL
-    amdil64,    // AMDIL with 64-bit pointers
-    hsail,      // AMD HSAIL
-    hsail64,    // AMD HSAIL with 64-bit pointers
-    spir,       // SPIR: standard portable IR for OpenCL 32-bit version
-    spir64,     // SPIR: standard portable IR for OpenCL 64-bit version
-    kalimba,    // Kalimba: generic kalimba
-    shave,      // SHAVE: Movidius vector VLIW processors
-    wasm32,     // WebAssembly with 32-bit pointers
-    wasm64,     // WebAssembly with 64-bit pointers
-    LastArchType = wasm64
-  };
-
-  enum SubArchType {
-    NoSubArch,
-
-    ARMSubArch_v8_1a,
-    ARMSubArch_v8,
-    ARMSubArch_v7,
-    ARMSubArch_v7em,
-    ARMSubArch_v7m,
-    ARMSubArch_v7s,
-    ARMSubArch_v6,
-    ARMSubArch_v6m,
-    ARMSubArch_v6k,
-    ARMSubArch_v6t2,
-    ARMSubArch_v5,
-    ARMSubArch_v5te,
-    ARMSubArch_v4t,
-
-    KalimbaSubArch_v3,
-    KalimbaSubArch_v4,
-    KalimbaSubArch_v5
-  };
-
-  enum VendorType {
-    UnknownVendor,
-
-    Apple,
-    PC,
-    SCEI,
-    BGP,
-    BGQ,
-    Freescale,
-    IBM,
-    ImaginationTechnologies,
-    MipsTechnologies,
-    NVIDIA,
-    CSR,
-    Myriad,
-    LastVendorType = Myriad
-  };
-
-  enum OSType {
-    UnknownOS,
-
-    CloudABI,
-    Darwin,
-    DragonFly,
-    FreeBSD,
-    IOS,
-    KFreeBSD,
-    Linux,
-    Lv2, // PS3
-    MacOSX,
-    NetBSD,
-    OpenBSD,
-    Solaris,
-    Win32,
-    Haiku,
-    Minix,
-    RTEMS,
-    NaCl, // Native Client
-    CNK,  // BG/P Compute-Node Kernel
-    Bitrig,
-    AIX,
-    CUDA,   // NVIDIA CUDA
-    NVCL,   // NVIDIA OpenCL
-    AMDHSA, // AMD HSA Runtime
-    PS4,
-    LastOSType = PS4
-  };
-
-  enum EnvironmentType {
-    UnknownEnvironment,
-
-    GNU,
-    GNUEABI,
-    GNUEABIHF,
-    GNUX32,
-    CODE16,
-    EABI,
-    EABIHF,
-    Android,
-
-    MSVC,
-    Itanium,
-    Cygnus,
-    AMDOpenCL,
-    CoreCLR,
-    LastEnvironmentType = CoreCLR
-  };
-
-  enum ObjectFormatType {
-    UnknownObjectFormat,
-
-    COFF,
-    ELF,
-    MachO,
-  };
-
-public:
-  /// @name Constructors
-  /// @{
-
-  /// Default constructor leaves all fields unknown.
-  TargetTuple() : GnuTT() {}
-
-  /// Convert a GNU Triple to a TargetTuple.
-  ///
-  /// This conversion assumes that GNU Triple's have a specific defined meaning
-  /// which isn't strictly true. A single Triple can potentially have multiple
-  /// contradictory meanings depending on compiler options and configure-time
-  /// options. Despite this, Triple's do tend to have a 'usual' meaning, or
-  /// rather a default behaviour and this function selects it.
-  ///
-  /// When tool options affect the desired TargetTuple, the tool should obtain
-  /// the usual meaning of the GNU Triple using this constructor and then use
-  /// the mutator methods to apply the tool options.
-  explicit TargetTuple(const Triple &GnuTT) : GnuTT(GnuTT) {}
-
-  /// @}
-  /// @name Typed Component Access
-  /// @{
-
-  /// Get the parsed architecture type of this triple.
-  ArchType getArch() const;
-
-  /// get the parsed subarchitecture type for this triple.
-  SubArchType getSubArch() const;
-
-  /// Get the parsed vendor type of this triple.
-  VendorType getVendor() const;
-
-  /// Get the parsed operating system type of this triple.
-  OSType getOS() const;
-
-  /// Does this triple have the optional environment
-  /// (fourth) component?
-  bool hasEnvironment() const { return GnuTT.hasEnvironment(); }
-
-  /// Get the parsed environment type of this triple.
-  EnvironmentType getEnvironment() const;
-
-  /// Parse the version number from the OS name component of the
-  /// triple, if present.
-  ///
-  /// For example, "fooos1.2.3" would return (1, 2, 3).
-  ///
-  /// If an entry is not defined, it will be returned as 0.
-  void getEnvironmentVersion(unsigned &Major, unsigned &Minor,
-                             unsigned &Micro) const;
-
-  /// Get the object format for this triple.
-  ObjectFormatType getObjectFormat() const;
-
-  /// Parse the version number from the OS name component of the
-  /// triple, if present.
-  ///
-  /// For example, "fooos1.2.3" would return (1, 2, 3).
-  ///
-  /// If an entry is not defined, it will be returned as 0.
-  void getOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) const {
-    return GnuTT.getOSVersion(Major, Minor, Micro);
-  }
-
-  /// Return just the major version number, this is
-  /// specialized because it is a common query.
-  unsigned getOSMajorVersion() const { return GnuTT.getOSMajorVersion(); }
-
-  /// Parse the version number as with getOSVersion and then
-  /// translate generic "darwin" versions to the corresponding OS X versions.
-  /// This may also be called with IOS triples but the OS X version number is
-  /// just set to a constant 10.4.0 in that case.  Returns true if successful.
-  bool getMacOSXVersion(unsigned &Major, unsigned &Minor,
-                        unsigned &Micro) const {
-    return GnuTT.getMacOSXVersion(Major, Minor, Micro);
-  }
-
-  /// Parse the version number as with getOSVersion.  This
-  /// should
-  /// only be called with IOS triples.
-  void getiOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) const {
-    return GnuTT.getiOSVersion(Major, Minor, Micro);
-  }
-
-  /// @}
-  /// @name Direct Component Access
-  /// @{
-
-  const std::string &str() const { return GnuTT.str(); }
-
-  const std::string &getTriple() const { return GnuTT.str(); }
-
-  /// Get the architecture (first) component of the
-  /// triple.
-  StringRef getArchName() const { return GnuTT.getArchName(); }
-
-  /// Get the vendor (second) component of the triple.
-  StringRef getVendorName() const { return GnuTT.getVendorName(); }
-
-  /// Get the operating system (third) component of the
-  /// triple.
-  StringRef getOSName() const { return GnuTT.getOSName(); }
-
-  /// Get the optional environment (fourth)
-  /// component of the triple, or "" if empty.
-  StringRef getEnvironmentName() const { return GnuTT.getEnvironmentName(); }
-
-  /// Get the operating system and optional
-  /// environment components as a single string (separated by a '-'
-  /// if the environment component is present).
-  StringRef getOSAndEnvironmentName() const {
-    return GnuTT.getOSAndEnvironmentName();
-  }
-
-  /// @}
-  /// @name Convenience Predicates
-  /// @{
-
-  /// Test whether the architecture is 64-bit
-  ///
-  /// Note that this tests for 64-bit pointer width, and nothing else. Note
-  /// that we intentionally expose only three predicates, 64-bit, 32-bit, and
-  /// 16-bit. The inner details of pointer width for particular architectures
-  /// is not summed up in the triple, and so only a coarse grained predicate
-  /// system is provided.
-  bool isArch64Bit() const { return GnuTT.isArch64Bit(); }
-
-  /// Test whether the architecture is 32-bit
-  ///
-  /// Note that this tests for 32-bit pointer width, and nothing else.
-  bool isArch32Bit() const { return GnuTT.isArch32Bit(); }
-
-  /// Test whether the architecture is 16-bit
-  ///
-  /// Note that this tests for 16-bit pointer width, and nothing else.
-  bool isArch16Bit() const { return GnuTT.isArch16Bit(); }
-
-  /// Helper function for doing comparisons against version
-  /// numbers included in the target triple.
-  bool isOSVersionLT(unsigned Major, unsigned Minor = 0,
-                     unsigned Micro = 0) const {
-    return GnuTT.isOSVersionLT(Major, Minor, Micro);
-  }
-
-  bool isOSVersionLT(const Triple &Other) const {
-    return GnuTT.isOSVersionLT(Other);
-  }
-
-  /// Comparison function for checking OS X version
-  /// compatibility, which handles supporting skewed version numbering schemes
-  /// used by the "darwin" triples.
-  unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0,
-                             unsigned Micro = 0) const {
-    return GnuTT.isMacOSXVersionLT(Major, Minor, Micro);
-  }
-
-  /// Is this a Mac OS X triple. For legacy reasons, we support both
-  /// "darwin" and "osx" as OS X triples.
-  bool isMacOSX() const { return GnuTT.isMacOSX(); }
-
-  /// Is this an iOS triple.
-  bool isiOS() const { return GnuTT.isiOS(); }
-
-  /// Is this a "Darwin" OS (OS X or iOS).
-  bool isOSDarwin() const { return GnuTT.isOSDarwin(); }
-
-  bool isOSNetBSD() const { return GnuTT.isOSNetBSD(); }
-
-  bool isOSOpenBSD() const { return GnuTT.isOSOpenBSD(); }
-
-  bool isOSFreeBSD() const { return GnuTT.isOSFreeBSD(); }
-
-  bool isOSDragonFly() const { return GnuTT.isOSDragonFly(); }
-
-  bool isOSSolaris() const { return GnuTT.isOSSolaris(); }
-
-  bool isOSBitrig() const { return GnuTT.isOSBitrig(); }
-
-  bool isWindowsMSVCEnvironment() const {
-    return GnuTT.isWindowsMSVCEnvironment();
-  }
-
-  bool isKnownWindowsMSVCEnvironment() const {
-    return GnuTT.isKnownWindowsMSVCEnvironment();
-  }
-
-  bool isWindowsCoreCLREnvironment() const {
-    return GnuTT.isWindowsCoreCLREnvironment();
-  }
-
-  bool isWindowsItaniumEnvironment() const {
-    return GnuTT.isWindowsItaniumEnvironment();
-  }
-
-  bool isWindowsCygwinEnvironment() const {
-    return GnuTT.isWindowsCygwinEnvironment();
-  }
-
-  bool isWindowsGNUEnvironment() const {
-    return GnuTT.isWindowsGNUEnvironment();
-  }
-
-  /// Tests for either Cygwin or MinGW OS
-  bool isOSCygMing() const { return GnuTT.isOSCygMing(); }
-
-  /// Is this a "Windows" OS targeting a "MSVCRT.dll" environment.
-  bool isOSMSVCRT() const { return GnuTT.isOSMSVCRT(); }
-
-  /// Tests whether the OS is Windows.
-  bool isOSWindows() const { return GnuTT.isOSWindows(); }
-
-  /// Tests whether the OS is NaCl (Native Client)
-  bool isOSNaCl() const { return GnuTT.isOSNaCl(); }
-
-  /// Tests whether the OS is Linux.
-  bool isOSLinux() const { return GnuTT.isOSLinux(); }
-
-  /// Tests whether the OS uses the ELF binary format.
-  bool isOSBinFormatELF() const { return GnuTT.isOSBinFormatELF(); }
-
-  /// Tests whether the OS uses the COFF binary format.
-  bool isOSBinFormatCOFF() const { return GnuTT.isOSBinFormatCOFF(); }
-
-  /// Tests whether the environment is MachO.
-  bool isOSBinFormatMachO() const { return GnuTT.isOSBinFormatMachO(); }
-
-  /// Tests whether the target is the PS4 CPU
-  bool isPS4CPU() const { return GnuTT.isPS4CPU(); }
-
-  /// Tests whether the target is the PS4 platform
-  bool isPS4() const { return GnuTT.isPS4(); }
-
-  /// @}
-
-  // FIXME: Remove. This function exists to avoid having to migrate everything
-  //        at once.
-  const Triple &getTargetTriple() const { return GnuTT; }
-
-private:
-  Triple GnuTT;
-};
-
-} // End llvm namespace
-
-#endif

Modified: llvm/trunk/include/llvm/MC/MCELFObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCELFObjectWriter.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCELFObjectWriter.h (original)
+++ llvm/trunk/include/llvm/MC/MCELFObjectWriter.h Tue Sep 15 11:17:27 2015
@@ -10,7 +10,7 @@
 #ifndef LLVM_MC_MCELFOBJECTWRITER_H
 #define LLVM_MC_MCELFOBJECTWRITER_H
 
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/Support/DataTypes.h"
 #include "llvm/Support/ELF.h"
 #include <vector>
@@ -50,17 +50,17 @@ protected:
                           bool IsN64=false);
 
 public:
-  static uint8_t getOSABI(TargetTuple::OSType OSType) {
+  static uint8_t getOSABI(Triple::OSType OSType) {
     switch (OSType) {
-    case TargetTuple::CloudABI:
-      return ELF::ELFOSABI_CLOUDABI;
-    case TargetTuple::PS4:
-    case TargetTuple::FreeBSD:
-      return ELF::ELFOSABI_FREEBSD;
-    case TargetTuple::Linux:
-      return ELF::ELFOSABI_LINUX;
-    default:
-      return ELF::ELFOSABI_NONE;
+      case Triple::CloudABI:
+        return ELF::ELFOSABI_CLOUDABI;
+      case Triple::PS4:
+      case Triple::FreeBSD:
+        return ELF::ELFOSABI_FREEBSD;
+      case Triple::Linux:
+        return ELF::ELFOSABI_LINUX;
+      default:
+        return ELF::ELFOSABI_NONE;
     }
   }
 

Modified: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSubtargetInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCSubtargetInfo.h Tue Sep 15 11:17:27 2015
@@ -14,7 +14,6 @@
 #ifndef LLVM_MC_MCSUBTARGETINFO_H
 #define LLVM_MC_MCSUBTARGETINFO_H
 
-#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include <string>
@@ -28,10 +27,10 @@ class StringRef;
 /// MCSubtargetInfo - Generic base class for all target subtargets.
 ///
 class MCSubtargetInfo {
-  TargetTuple TheTargetTuple;                 // Target triple
-  std::string CPU;                            // CPU being targeted.
+  Triple TargetTriple;                        // Target triple
+  std::string CPU; // CPU being targeted.
   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
-  ArrayRef<SubtargetFeatureKV> ProcDesc;      // Processor descriptions
+  ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
 
   // Scheduler machine model
   const SubtargetInfoKV *ProcSchedModels;
@@ -51,7 +50,7 @@ class MCSubtargetInfo {
 
 public:
   MCSubtargetInfo(const MCSubtargetInfo &) = default;
-  MCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS,
+  MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
                   ArrayRef<SubtargetFeatureKV> PF,
                   ArrayRef<SubtargetFeatureKV> PD,
                   const SubtargetInfoKV *ProcSched,
@@ -59,8 +58,8 @@ public:
                   const MCReadAdvanceEntry *RA, const InstrStage *IS,
                   const unsigned *OC, const unsigned *FP);
 
-  /// getTargetTuple - Return the target triple string.
-  const TargetTuple &getTargetTuple() const { return TheTargetTuple; }
+  /// getTargetTriple - Return the target triple string.
+  const Triple &getTargetTriple() const { return TargetTriple; }
 
   /// getCPU - Return the CPU string.
   StringRef getCPU() const {

Modified: llvm/trunk/include/llvm/Support/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetRegistry.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetRegistry.h (original)
+++ llvm/trunk/include/llvm/Support/TargetRegistry.h Tue Sep 15 11:17:27 2015
@@ -21,7 +21,6 @@
 
 #include "llvm-c/Disassembler.h"
 #include "llvm/ADT/Triple.h"
-#include "llvm/ADT/TargetTuple.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/FormattedStream.h"
 #include <cassert>
@@ -70,10 +69,9 @@ MCStreamer *createMachOStreamer(MCContex
                                 bool RelaxAll, bool DWARFMustBeAtTheEnd,
                                 bool LabelSections = false);
 
-MCRelocationInfo *createMCRelocationInfo(const TargetTuple &TT, MCContext &Ctx);
+MCRelocationInfo *createMCRelocationInfo(const Triple &TT, MCContext &Ctx);
 
-MCSymbolizer *createMCSymbolizer(const TargetTuple &TT,
-                                 LLVMOpInfoCallback GetOpInfo,
+MCSymbolizer *createMCSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
                                  LLVMSymbolLookupCallback SymbolLookUp,
                                  void *DisInfo, MCContext *Ctx,
                                  std::unique_ptr<MCRelocationInfo> &&RelInfo);
@@ -93,21 +91,19 @@ public:
   typedef bool (*ArchMatchFnTy)(Triple::ArchType Arch);
 
   typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI,
-                                          const TargetTuple &TT);
-  typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const TargetTuple &TT,
+                                          const Triple &TT);
+  typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const Triple &TT,
                                                   Reloc::Model RM,
                                                   CodeModel::Model CM,
                                                   CodeGenOpt::Level OL);
   typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
   typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info);
-  typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(const TargetTuple &TT);
-  // FIXME: CPU and Features should be merged into TargetTuple when possible.
-  typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const TargetTuple &TT,
+  typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(const Triple &TT);
+  typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const Triple &TT,
                                                       StringRef CPU,
                                                       StringRef Features);
-  // FIXME: CPU and Features should be merged into TargetTuple when possible.
   typedef TargetMachine *(*TargetMachineCtorTy)(
-      const Target &T, const TargetTuple &TT, StringRef CPU, StringRef Features,
+      const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
       const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
       CodeGenOpt::Level OL);
   // If it weren't for layering issues (this header is in llvm/Support, but
@@ -115,18 +111,16 @@ public:
   // reference.
   typedef AsmPrinter *(*AsmPrinterCtorTy)(
       TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
-  // FIXME: CPU and Features should be merged into TargetTuple when possible.
   typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
                                               const MCRegisterInfo &MRI,
-                                              const TargetTuple &TT,
-                                              StringRef CPU);
+                                              const Triple &TT, StringRef CPU);
   typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(
       MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
       const MCTargetOptions &Options);
   typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,
                                                   const MCSubtargetInfo &STI,
                                                   MCContext &Ctx);
-  typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const TargetTuple &T,
+  typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Triple &T,
                                                 unsigned SyntaxVariant,
                                                 const MCAsmInfo &MAI,
                                                 const MCInstrInfo &MII,
@@ -134,7 +128,7 @@ public:
   typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,
                                                 const MCRegisterInfo &MRI,
                                                 MCContext &Ctx);
-  typedef MCStreamer *(*ELFStreamerCtorTy)(const TargetTuple &T, MCContext &Ctx,
+  typedef MCStreamer *(*ELFStreamerCtorTy)(const Triple &T, MCContext &Ctx,
                                            MCAsmBackend &TAB,
                                            raw_pwrite_stream &OS,
                                            MCCodeEmitter *Emitter,
@@ -154,10 +148,10 @@ public:
       bool IsVerboseAsm);
   typedef MCTargetStreamer *(*ObjectTargetStreamerCtorTy)(
       MCStreamer &S, const MCSubtargetInfo &STI);
-  typedef MCRelocationInfo *(*MCRelocationInfoCtorTy)(const TargetTuple &TT,
+  typedef MCRelocationInfo *(*MCRelocationInfoCtorTy)(const Triple &TT,
                                                       MCContext &Ctx);
   typedef MCSymbolizer *(*MCSymbolizerCtorTy)(
-      const TargetTuple &TT, LLVMOpInfoCallback GetOpInfo,
+      const Triple &TT, LLVMOpInfoCallback GetOpInfo,
       LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx,
       std::unique_ptr<MCRelocationInfo> &&RelInfo);
 
@@ -294,14 +288,15 @@ public:
   /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified
   /// target triple.
   ///
-  /// \param TT This argument is used to determine the target machine
+  /// \param TheTriple This argument is used to determine the target machine
   /// feature set; it should always be provided. Generally this should be
   /// either the target triple from the module, or the target triple of the
   /// host if that does not exist.
-  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) const {
+  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
+                             StringRef TheTriple) const {
     if (!MCAsmInfoCtorFn)
       return nullptr;
-    return MCAsmInfoCtorFn(MRI, TargetTuple(Triple(TT)));
+    return MCAsmInfoCtorFn(MRI, Triple(TheTriple));
   }
 
   /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
@@ -311,7 +306,7 @@ public:
                                      CodeGenOpt::Level OL) const {
     if (!MCCodeGenInfoCtorFn)
       return nullptr;
-    return MCCodeGenInfoCtorFn(TargetTuple(Triple(TT)), RM, CM, OL);
+    return MCCodeGenInfoCtorFn(Triple(TT), RM, CM, OL);
   }
 
   /// createMCInstrInfo - Create a MCInstrInfo implementation.
@@ -335,27 +330,27 @@ public:
   MCRegisterInfo *createMCRegInfo(StringRef TT) const {
     if (!MCRegInfoCtorFn)
       return nullptr;
-    return MCRegInfoCtorFn(TargetTuple(Triple(TT)));
+    return MCRegInfoCtorFn(Triple(TT));
   }
 
   /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
   ///
-  /// \param TT This argument is used to determine the target machine
+  /// \param TheTriple This argument is used to determine the target machine
   /// feature set; it should always be provided. Generally this should be
   /// either the target triple from the module, or the target triple of the
   /// host if that does not exist.
   /// \param CPU This specifies the name of the target CPU.
   /// \param Features This specifies the string representation of the
   /// additional target features.
-  MCSubtargetInfo *createMCSubtargetInfo(StringRef TT, StringRef CPU,
+  MCSubtargetInfo *createMCSubtargetInfo(StringRef TheTriple, StringRef CPU,
                                          StringRef Features) const {
     if (!MCSubtargetInfoCtorFn)
       return nullptr;
-    return MCSubtargetInfoCtorFn(TargetTuple(Triple(TT)), CPU, Features);
+    return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features);
   }
 
   /// createTargetMachine - Create a target specific machine implementation
-  /// for the specified \p TT.
+  /// for the specified \p Triple.
   ///
   /// \param TT This argument is used to determine the target machine
   /// feature set; it should always be provided. Generally this should be
@@ -369,18 +364,18 @@ public:
                       CodeGenOpt::Level OL = CodeGenOpt::Default) const {
     if (!TargetMachineCtorFn)
       return nullptr;
-    return TargetMachineCtorFn(*this, TargetTuple(Triple(TT)), CPU, Features,
-                               Options, RM, CM, OL);
+    return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
+                               CM, OL);
   }
 
   /// createMCAsmBackend - Create a target specific assembly parser.
   ///
-  /// \param TT The target triple string.
-  MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, StringRef TT,
-                                   StringRef CPU) const {
+  /// \param TheTriple The target triple string.
+  MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
+                                   StringRef TheTriple, StringRef CPU) const {
     if (!MCAsmBackendCtorFn)
       return nullptr;
-    return MCAsmBackendCtorFn(*this, MRI, TargetTuple(Triple(TT)), CPU);
+    return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU);
   }
 
   /// createMCAsmParser - Create a target specific assembly parser.
@@ -412,14 +407,13 @@ public:
     return MCDisassemblerCtorFn(*this, STI, Ctx);
   }
 
-  MCInstPrinter *createMCInstPrinter(const TargetTuple &TT,
-                                     unsigned SyntaxVariant,
+  MCInstPrinter *createMCInstPrinter(const Triple &T, unsigned SyntaxVariant,
                                      const MCAsmInfo &MAI,
                                      const MCInstrInfo &MII,
                                      const MCRegisterInfo &MRI) const {
     if (!MCInstPrinterCtorFn)
       return nullptr;
-    return MCInstPrinterCtorFn(TT, SyntaxVariant, MAI, MII, MRI);
+    return MCInstPrinterCtorFn(T, SyntaxVariant, MAI, MII, MRI);
   }
 
   /// createMCCodeEmitter - Create a target specific code emitter.
@@ -433,26 +427,26 @@ public:
 
   /// Create a target specific MCStreamer.
   ///
-  /// \param TT The target triple.
+  /// \param T The target triple.
   /// \param Ctx The target context.
   /// \param TAB The target assembler backend object. Takes ownership.
   /// \param OS The stream object.
   /// \param Emitter The target independent assembler object.Takes ownership.
   /// \param RelaxAll Relax all fixups?
-  MCStreamer *createMCObjectStreamer(const TargetTuple &TT, MCContext &Ctx,
+  MCStreamer *createMCObjectStreamer(const Triple &T, MCContext &Ctx,
                                      MCAsmBackend &TAB, raw_pwrite_stream &OS,
                                      MCCodeEmitter *Emitter,
                                      const MCSubtargetInfo &STI, bool RelaxAll,
                                      bool DWARFMustBeAtTheEnd) const {
     MCStreamer *S;
-    switch (TT.getObjectFormat()) {
+    switch (T.getObjectFormat()) {
     default:
       llvm_unreachable("Unknown object format");
-    case TargetTuple::COFF:
-      assert(TT.isOSWindows() && "only Windows COFF is supported");
+    case Triple::COFF:
+      assert(T.isOSWindows() && "only Windows COFF is supported");
       S = COFFStreamerCtorFn(Ctx, TAB, OS, Emitter, RelaxAll);
       break;
-    case TargetTuple::MachO:
+    case Triple::MachO:
       if (MachOStreamerCtorFn)
         S = MachOStreamerCtorFn(Ctx, TAB, OS, Emitter, RelaxAll,
                                 DWARFMustBeAtTheEnd);
@@ -460,9 +454,9 @@ public:
         S = createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
                                 DWARFMustBeAtTheEnd);
       break;
-    case TargetTuple::ELF:
+    case Triple::ELF:
       if (ELFStreamerCtorFn)
-        S = ELFStreamerCtorFn(TT, Ctx, TAB, OS, Emitter, RelaxAll);
+        S = ELFStreamerCtorFn(T, Ctx, TAB, OS, Emitter, RelaxAll);
       else
         S = createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
       break;
@@ -514,7 +508,7 @@ public:
     MCRelocationInfoCtorTy Fn = MCRelocationInfoCtorFn
                                     ? MCRelocationInfoCtorFn
                                     : llvm::createMCRelocationInfo;
-    return Fn(TargetTuple(Triple(TT)), Ctx);
+    return Fn(Triple(TT), Ctx);
   }
 
   /// createMCSymbolizer - Create a target specific MCSymbolizer.
@@ -536,7 +530,7 @@ public:
                      std::unique_ptr<MCRelocationInfo> &&RelInfo) const {
     MCSymbolizerCtorTy Fn =
         MCSymbolizerCtorFn ? MCSymbolizerCtorFn : llvm::createMCSymbolizer;
-    return Fn(TargetTuple(Triple(TT)), GetOpInfo, SymbolLookUp, DisInfo, Ctx,
+    return Fn(Triple(TT), GetOpInfo, SymbolLookUp, DisInfo, Ctx,
               std::move(RelInfo));
   }
 
@@ -594,10 +588,11 @@ struct TargetRegistry {
 
   /// lookupTarget - Lookup a target based on a target triple.
   ///
-  /// \param TT - The triple to use for finding a target.
+  /// \param Triple - The triple to use for finding a target.
   /// \param Error - On failure, an error string describing why no target was
   /// found.
-  static const Target *lookupTarget(const std::string &TT, std::string &Error);
+  static const Target *lookupTarget(const std::string &Triple,
+                                    std::string &Error);
 
   /// lookupTarget - Lookup a target based on an architecture name
   /// and a target triple.  If the architecture name is non-empty,
@@ -605,13 +600,13 @@ struct TargetRegistry {
   /// triple is used.
   ///
   /// \param ArchName - The architecture to use for finding a target.
-  /// \param TT - The triple to use for finding a target.  The
+  /// \param TheTriple - The triple to use for finding a target.  The
   /// triple is updated with canonical architecture name if a lookup
   /// by architecture is done.
   /// \param Error - On failure, an error string describing why no target was
   /// found.
-  static const Target *lookupTarget(const std::string &ArchName, Triple &TT,
-                                    std::string &Error);
+  static const Target *lookupTarget(const std::string &ArchName,
+                                    Triple &TheTriple, std::string &Error);
 
   /// @}
   /// @name Target Registration
@@ -897,8 +892,8 @@ template <class MCAsmInfoImpl> struct Re
 
 private:
   static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/,
-                              const TargetTuple &TT) {
-    return new MCAsmInfoImpl(TargetTuple(TT));
+                              const Triple &TT) {
+    return new MCAsmInfoImpl(TT);
   }
 };
 
@@ -931,8 +926,8 @@ template <class MCCodeGenInfoImpl> struc
   }
 
 private:
-  static MCCodeGenInfo *Allocator(const TargetTuple & /*TT*/,
-                                  Reloc::Model /*RM*/, CodeModel::Model /*CM*/,
+  static MCCodeGenInfo *Allocator(const Triple & /*TT*/, Reloc::Model /*RM*/,
+                                  CodeModel::Model /*CM*/,
                                   CodeGenOpt::Level /*OL*/) {
     return new MCCodeGenInfoImpl();
   }
@@ -1030,7 +1025,7 @@ template <class MCRegisterInfoImpl> stru
   }
 
 private:
-  static MCRegisterInfo *Allocator(const TargetTuple & /*TT*/) {
+  static MCRegisterInfo *Allocator(const Triple & /*TT*/) {
     return new MCRegisterInfoImpl();
   }
 };
@@ -1063,8 +1058,8 @@ template <class MCSubtargetInfoImpl> str
   }
 
 private:
-  static MCSubtargetInfo *Allocator(const TargetTuple & /*TT*/,
-                                    StringRef /*CPU*/, StringRef /*FS*/) {
+  static MCSubtargetInfo *Allocator(const Triple & /*TT*/, StringRef /*CPU*/,
+                                    StringRef /*FS*/) {
     return new MCSubtargetInfoImpl();
   }
 };
@@ -1097,12 +1092,11 @@ template <class TargetMachineImpl> struc
   }
 
 private:
-  static TargetMachine *Allocator(const Target &T, const TargetTuple &TT,
+  static TargetMachine *Allocator(const Target &T, const Triple &TT,
                                   StringRef CPU, StringRef FS,
                                   const TargetOptions &Options, Reloc::Model RM,
                                   CodeModel::Model CM, CodeGenOpt::Level OL) {
-    return new TargetMachineImpl(T, TT.getTargetTriple(), CPU, FS, Options, RM,
-                                 CM, OL);
+    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
   }
 };
 
@@ -1120,8 +1114,8 @@ template <class MCAsmBackendImpl> struct
 
 private:
   static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI,
-                                 const TargetTuple &TT, StringRef CPU) {
-    return new MCAsmBackendImpl(T, MRI, TT, CPU);
+                                 const Triple &TheTriple, StringRef CPU) {
+    return new MCAsmBackendImpl(T, MRI, TheTriple, CPU);
   }
 };
 

Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Tue Sep 15 11:17:27 2015
@@ -15,7 +15,6 @@
 #define LLVM_TARGET_TARGETMACHINE_H
 
 #include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/TargetTuple.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Pass.h"
@@ -117,8 +116,6 @@ public:
   const Target &getTarget() const { return TheTarget; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
-  // FIXME: Return a reference once we store a TargetTuple
-  const TargetTuple getTargetTuple() const { return TargetTuple(TargetTriple); }
   StringRef getTargetCPU() const { return TargetCPU; }
   StringRef getTargetFeatureString() const { return TargetFS; }
 

Modified: llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h Tue Sep 15 11:17:27 2015
@@ -48,7 +48,7 @@ class TargetSubtargetInfo : public MCSub
   TargetSubtargetInfo() = delete;
 
 protected: // Can only create subclasses...
-  TargetSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS,
+  TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
                       ArrayRef<SubtargetFeatureKV> PF,
                       ArrayRef<SubtargetFeatureKV> PD,
                       const SubtargetInfoKV *ProcSched,

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Tue Sep 15 11:17:27 2015
@@ -170,7 +170,7 @@ bool LLVMTargetMachine::addPassesToEmitF
   switch (FileType) {
   case CGFT_AssemblyFile: {
     MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter(
-        getTargetTuple(), MAI.getAssemblerDialect(), MAI, MII, MRI);
+        getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI);
 
     // Create a code emitter if asked to show the encoding.
     MCCodeEmitter *MCE = nullptr;
@@ -199,7 +199,7 @@ bool LLVMTargetMachine::addPassesToEmitF
     // Don't waste memory on names of temp labels.
     Context->setUseNamesOnTempLabels(false);
 
-    TargetTuple T(Triple(getTargetTriple().str()));
+    Triple T(getTargetTriple().str());
     AsmStreamer.reset(getTarget().createMCObjectStreamer(
         T, *Context, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
         /*DWARFMustBeAtTheEnd*/ true));
@@ -250,10 +250,10 @@ bool LLVMTargetMachine::addPassesToEmitM
   if (!MCE || !MAB)
     return true;
 
-  const TargetTuple &TT = getTargetTuple();
+  const Triple &T = getTargetTriple();
   const MCSubtargetInfo &STI = *getMCSubtargetInfo();
   std::unique_ptr<MCStreamer> AsmStreamer(getTarget().createMCObjectStreamer(
-      TT, *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
+      T, *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
       /*DWARFMustBeAtTheEnd*/ true));
 
   // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.

Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Tue Sep 15 11:17:27 2015
@@ -83,7 +83,7 @@ LLVMCreateDisasmCPUFeatures(const char *
   // Set up the instruction printer.
   int AsmPrinterVariant = MAI->getAssemblerDialect();
   MCInstPrinter *IP = TheTarget->createMCInstPrinter(
-      TargetTuple(Triple(TT)), AsmPrinterVariant, *MAI, *MII, *MRI);
+      Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI);
   if (!IP)
     return nullptr;
 
@@ -310,8 +310,7 @@ int LLVMSetDisasmOptions(LLVMDisasmConte
       int AsmPrinterVariant = MAI->getAssemblerDialect();
       AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
       MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter(
-          TargetTuple(Triple(DC->getTripleName())), AsmPrinterVariant, *MAI,
-          *MII, *MRI);
+          Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
       if (IP) {
         DC->setIP(IP);
         DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);

Modified: llvm/trunk/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp Tue Sep 15 11:17:27 2015
@@ -17,7 +17,7 @@
 using namespace llvm;
 
 namespace llvm {
-class TargetTuple;
+class Triple;
 }
 
 // This function tries to add a symbolic operand in place of the immediate
@@ -188,8 +188,7 @@ void MCExternalSymbolizer::tryAddingPcLo
 }
 
 namespace llvm {
-MCSymbolizer *createMCSymbolizer(const TargetTuple &TT,
-                                 LLVMOpInfoCallback GetOpInfo,
+MCSymbolizer *createMCSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
                                  LLVMSymbolLookupCallback SymbolLookUp,
                                  void *DisInfo, MCContext *Ctx,
                                  std::unique_ptr<MCRelocationInfo> &&RelInfo) {

Modified: llvm/trunk/lib/MC/MCDisassembler/MCRelocationInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/MCRelocationInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/MCRelocationInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/MCRelocationInfo.cpp Tue Sep 15 11:17:27 2015
@@ -34,7 +34,7 @@ MCRelocationInfo::createExprForCAPIVaria
   return SubExpr;
 }
 
-MCRelocationInfo *llvm::createMCRelocationInfo(const TargetTuple &TT,
+MCRelocationInfo *llvm::createMCRelocationInfo(const Triple &TT,
                                                MCContext &Ctx) {
   return new MCRelocationInfo(Ctx);
 }

Modified: llvm/trunk/lib/MC/MCSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSubtargetInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCSubtargetInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCSubtargetInfo.cpp Tue Sep 15 11:17:27 2015
@@ -9,7 +9,7 @@
 
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/raw_ostream.h"
@@ -37,12 +37,12 @@ void MCSubtargetInfo::setDefaultFeatures
 }
 
 MCSubtargetInfo::MCSubtargetInfo(
-    const TargetTuple &TT, StringRef C, StringRef FS,
+    const Triple &TT, StringRef C, StringRef FS,
     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
     const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
     const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
     const InstrStage *IS, const unsigned *OC, const unsigned *FP)
-    : TheTargetTuple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
+    : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
       ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
       ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
   InitMCProcessorInfo(CPU, FS);

Modified: llvm/trunk/lib/Support/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CMakeLists.txt?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Support/CMakeLists.txt (original)
+++ llvm/trunk/lib/Support/CMakeLists.txt Tue Sep 15 11:17:27 2015
@@ -88,7 +88,6 @@ add_llvm_library(LLVMSupport
   StringRef.cpp
   SystemUtils.cpp
   TargetParser.cpp
-  TargetTuple.cpp
   Timer.cpp
   ToolOutputFile.cpp
   Triple.cpp

Removed: llvm/trunk/lib/Support/TargetTuple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetTuple.cpp?rev=247701&view=auto
==============================================================================
--- llvm/trunk/lib/Support/TargetTuple.cpp (original)
+++ llvm/trunk/lib/Support/TargetTuple.cpp (removed)
@@ -1,315 +0,0 @@
-//===--- TargetTuple.cpp - Target tuple class -----------------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/ADT/StringSwitch.h"
-#include "llvm/ADT/TargetTuple.h"
-#include "llvm/Support/TargetParser.h"
-
-using namespace llvm;
-
-// FIXME: These should be removed as soon as the Triple member is replaced.
-static TargetTuple::ArchType
-convertTripleArchToTupleArch(Triple::ArchType Arch) {
-  switch (Arch) {
-  case Triple::UnknownArch:
-    return TargetTuple::UnknownArch;
-  case Triple::arm:
-    return TargetTuple::arm;
-  case Triple::armeb:
-    return TargetTuple::armeb;
-  case Triple::aarch64:
-    return TargetTuple::aarch64;
-  case Triple::aarch64_be:
-    return TargetTuple::aarch64_be;
-  case Triple::bpfel:
-    return TargetTuple::bpfel;
-  case Triple::bpfeb:
-    return TargetTuple::bpfeb;
-  case Triple::hexagon:
-    return TargetTuple::hexagon;
-  case Triple::mips:
-    return TargetTuple::mips;
-  case Triple::mipsel:
-    return TargetTuple::mipsel;
-  case Triple::mips64:
-    return TargetTuple::mips64;
-  case Triple::mips64el:
-    return TargetTuple::mips64el;
-  case Triple::msp430:
-    return TargetTuple::msp430;
-  case Triple::ppc:
-    return TargetTuple::ppc;
-  case Triple::ppc64:
-    return TargetTuple::ppc64;
-  case Triple::ppc64le:
-    return TargetTuple::ppc64le;
-  case Triple::r600:
-    return TargetTuple::r600;
-  case Triple::amdgcn:
-    return TargetTuple::amdgcn;
-  case Triple::sparc:
-    return TargetTuple::sparc;
-  case Triple::sparcv9:
-    return TargetTuple::sparcv9;
-  case Triple::sparcel:
-    return TargetTuple::sparcel;
-  case Triple::systemz:
-    return TargetTuple::systemz;
-  case Triple::tce:
-    return TargetTuple::tce;
-  case Triple::thumb:
-    return TargetTuple::thumb;
-  case Triple::thumbeb:
-    return TargetTuple::thumbeb;
-  case Triple::x86:
-    return TargetTuple::x86;
-  case Triple::x86_64:
-    return TargetTuple::x86_64;
-  case Triple::xcore:
-    return TargetTuple::xcore;
-  case Triple::nvptx:
-    return TargetTuple::nvptx;
-  case Triple::nvptx64:
-    return TargetTuple::nvptx64;
-  case Triple::le32:
-    return TargetTuple::le32;
-  case Triple::le64:
-    return TargetTuple::le64;
-  case Triple::amdil:
-    return TargetTuple::amdil;
-  case Triple::amdil64:
-    return TargetTuple::amdil64;
-  case Triple::hsail:
-    return TargetTuple::hsail;
-  case Triple::hsail64:
-    return TargetTuple::hsail64;
-  case Triple::spir:
-    return TargetTuple::spir;
-  case Triple::spir64:
-    return TargetTuple::spir64;
-  case Triple::kalimba:
-    return TargetTuple::kalimba;
-  case Triple::shave:
-    return TargetTuple::shave;
-  case Triple::wasm32:
-    return TargetTuple::wasm32;
-  case Triple::wasm64:
-    return TargetTuple::wasm64;
-  }
-  llvm_unreachable("Unmapped architecture.");
-}
-
-// FIXME: These should be removed as soon as the Triple member is replaced.
-static TargetTuple::SubArchType
-convertTripleSubArchToTupleSubArch(Triple::SubArchType SubArch) {
-  switch (SubArch) {
-  case Triple::NoSubArch:
-    return TargetTuple::NoSubArch;
-  case Triple::ARMSubArch_v8_1a:
-    return TargetTuple::ARMSubArch_v8_1a;
-  case Triple::ARMSubArch_v8:
-    return TargetTuple::ARMSubArch_v8;
-  case Triple::ARMSubArch_v7:
-    return TargetTuple::ARMSubArch_v7;
-  case Triple::ARMSubArch_v7em:
-    return TargetTuple::ARMSubArch_v7em;
-  case Triple::ARMSubArch_v7m:
-    return TargetTuple::ARMSubArch_v7m;
-  case Triple::ARMSubArch_v7s:
-    return TargetTuple::ARMSubArch_v7s;
-  case Triple::ARMSubArch_v6:
-    return TargetTuple::ARMSubArch_v6;
-  case Triple::ARMSubArch_v6m:
-    return TargetTuple::ARMSubArch_v6m;
-  case Triple::ARMSubArch_v6k:
-    return TargetTuple::ARMSubArch_v6k;
-  case Triple::ARMSubArch_v6t2:
-    return TargetTuple::ARMSubArch_v6t2;
-  case Triple::ARMSubArch_v5:
-    return TargetTuple::ARMSubArch_v5;
-  case Triple::ARMSubArch_v5te:
-    return TargetTuple::ARMSubArch_v5te;
-  case Triple::ARMSubArch_v4t:
-    return TargetTuple::ARMSubArch_v4t;
-  case Triple::KalimbaSubArch_v3:
-    return TargetTuple::KalimbaSubArch_v3;
-  case Triple::KalimbaSubArch_v4:
-    return TargetTuple::KalimbaSubArch_v4;
-  case Triple::KalimbaSubArch_v5:
-    return TargetTuple::KalimbaSubArch_v5;
-  }
-  llvm_unreachable("Unmapped subarchitecture.");
-}
-
-// FIXME: These should be removed as soon as the Triple member is replaced.
-static TargetTuple::VendorType
-convertTripleVendorToTupleVendor(Triple::VendorType Vendor) {
-  switch (Vendor) {
-  case Triple::UnknownVendor:
-    return TargetTuple::UnknownVendor;
-  case Triple::Apple:
-    return TargetTuple::Apple;
-  case Triple::PC:
-    return TargetTuple::PC;
-  case Triple::SCEI:
-    return TargetTuple::SCEI;
-  case Triple::BGP:
-    return TargetTuple::BGP;
-  case Triple::BGQ:
-    return TargetTuple::BGQ;
-  case Triple::Freescale:
-    return TargetTuple::Freescale;
-  case Triple::IBM:
-    return TargetTuple::IBM;
-  case Triple::ImaginationTechnologies:
-    return TargetTuple::ImaginationTechnologies;
-  case Triple::MipsTechnologies:
-    return TargetTuple::MipsTechnologies;
-  case Triple::NVIDIA:
-    return TargetTuple::NVIDIA;
-  case Triple::CSR:
-    return TargetTuple::CSR;
-  case Triple::Myriad:
-    return TargetTuple::Myriad;
-  }
-  llvm_unreachable("Unmapped vendor.");
-}
-
-// FIXME: These should be removed as soon as the Triple member is replaced.
-static TargetTuple::OSType convertTripleOSToTupleOS(Triple::OSType OS) {
-  switch (OS) {
-  case Triple::UnknownOS:
-    return TargetTuple::UnknownOS;
-  case Triple::CloudABI:
-    return TargetTuple::CloudABI;
-  case Triple::Darwin:
-    return TargetTuple::Darwin;
-  case Triple::DragonFly:
-    return TargetTuple::DragonFly;
-  case Triple::FreeBSD:
-    return TargetTuple::FreeBSD;
-  case Triple::IOS:
-    return TargetTuple::IOS;
-  case Triple::KFreeBSD:
-    return TargetTuple::KFreeBSD;
-  case Triple::Linux:
-    return TargetTuple::Linux;
-  case Triple::Lv2:
-    return TargetTuple::Lv2;
-  case Triple::MacOSX:
-    return TargetTuple::MacOSX;
-  case Triple::NetBSD:
-    return TargetTuple::NetBSD;
-  case Triple::OpenBSD:
-    return TargetTuple::OpenBSD;
-  case Triple::Solaris:
-    return TargetTuple::Solaris;
-  case Triple::Win32:
-    return TargetTuple::Win32;
-  case Triple::Haiku:
-    return TargetTuple::Haiku;
-  case Triple::Minix:
-    return TargetTuple::Minix;
-  case Triple::RTEMS:
-    return TargetTuple::RTEMS;
-  case Triple::NaCl:
-    return TargetTuple::NaCl;
-  case Triple::CNK:
-    return TargetTuple::CNK;
-  case Triple::Bitrig:
-    return TargetTuple::Bitrig;
-  case Triple::AIX:
-    return TargetTuple::AIX;
-  case Triple::CUDA:
-    return TargetTuple::CUDA;
-  case Triple::NVCL:
-    return TargetTuple::NVCL;
-  case Triple::AMDHSA:
-    return TargetTuple::AMDHSA;
-  case Triple::PS4:
-    return TargetTuple::PS4;
-  }
-  llvm_unreachable("Unmapped OS.");
-}
-
-// FIXME: These should be removed as soon as the Triple member is replaced.
-static TargetTuple::EnvironmentType
-convertTripleEnvToTupleEnv(Triple::EnvironmentType Env) {
-  switch (Env) {
-  case Triple::UnknownEnvironment:
-    return TargetTuple::UnknownEnvironment;
-  case Triple::GNU:
-    return TargetTuple::GNU;
-  case Triple::GNUEABI:
-    return TargetTuple::GNUEABI;
-  case Triple::GNUEABIHF:
-    return TargetTuple::GNUEABIHF;
-  case Triple::GNUX32:
-    return TargetTuple::GNUX32;
-  case Triple::CODE16:
-    return TargetTuple::CODE16;
-  case Triple::EABI:
-    return TargetTuple::EABI;
-  case Triple::EABIHF:
-    return TargetTuple::EABIHF;
-  case Triple::Android:
-    return TargetTuple::Android;
-  case Triple::MSVC:
-    return TargetTuple::MSVC;
-  case Triple::Itanium:
-    return TargetTuple::Itanium;
-  case Triple::Cygnus:
-    return TargetTuple::Cygnus;
-  case Triple::AMDOpenCL:
-    return TargetTuple::AMDOpenCL;
-  case Triple::CoreCLR:
-    return TargetTuple::CoreCLR;
-  }
-  llvm_unreachable("Unmapped Environment.");
-}
-
-// FIXME: These should be removed as soon as the Triple member is replaced.
-static TargetTuple::ObjectFormatType
-convertTripleObjFmtToTupleObjFmt(Triple::ObjectFormatType ObjFmt) {
-  switch (ObjFmt) {
-  case Triple::UnknownObjectFormat:
-    return TargetTuple::UnknownObjectFormat;
-  case Triple::COFF:
-    return TargetTuple::COFF;
-  case Triple::ELF:
-    return TargetTuple::ELF;
-  case Triple::MachO:
-    return TargetTuple::MachO;
-  }
-  llvm_unreachable("Unmapped Object Format.");
-}
-
-TargetTuple::ArchType TargetTuple::getArch() const {
-  return convertTripleArchToTupleArch(GnuTT.getArch());
-}
-
-TargetTuple::SubArchType TargetTuple::getSubArch() const {
-  return convertTripleSubArchToTupleSubArch(GnuTT.getSubArch());
-}
-
-TargetTuple::VendorType TargetTuple::getVendor() const {
-  return convertTripleVendorToTupleVendor(GnuTT.getVendor());
-}
-
-TargetTuple::OSType TargetTuple::getOS() const {
-  return convertTripleOSToTupleOS(GnuTT.getOS());
-}
-
-TargetTuple::EnvironmentType TargetTuple::getEnvironment() const {
-  return convertTripleEnvToTupleEnv(GnuTT.getEnvironment());
-}
-
-TargetTuple::ObjectFormatType TargetTuple::getObjectFormat() const {
-  return convertTripleObjFmtToTupleObjFmt(GnuTT.getObjectFormat());
-}

Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp Tue Sep 15 11:17:27 2015
@@ -45,7 +45,7 @@ AArch64Subtarget::initializeSubtargetDep
 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
                                    const TargetMachine &TM, bool LittleEndian)
-    : AArch64GenSubtargetInfo(TargetTuple(TT), CPU, FS), ARMProcFamily(Others),
+    : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
       HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false),
       HasCRC(false), HasPerfMon(false), HasZeroCycleRegMove(false),
       HasZeroCycleZeroing(false), StrictAlign(false), ReserveX18(false),

Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Tue Sep 15 11:17:27 2015
@@ -19,7 +19,6 @@
 #include "AArch64InstrInfo.h"
 #include "AArch64RegisterInfo.h"
 #include "AArch64SelectionDAGInfo.h"
-#include "llvm/ADT/TargetTuple.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 #include <string>
@@ -98,8 +97,6 @@ public:
     return &getInstrInfo()->getRegisterInfo();
   }
   const Triple &getTargetTriple() const { return TargetTriple; }
-  // FIXME: Return a references once our member is a TargetTuple.
-  const TargetTuple getTargetTuple() const { return TargetTuple(TargetTriple); }
   bool enableMachineScheduler() const override { return true; }
   bool enablePostRAScheduler() const override {
     return isCortexA53() || isCortexA57();

Modified: llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Tue Sep 15 11:17:27 2015
@@ -227,10 +227,11 @@ DecodeStatus AArch64Disassembler::getIns
   return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
 }
 
-static MCSymbolizer *createAArch64ExternalSymbolizer(
-    const TargetTuple &TT, LLVMOpInfoCallback GetOpInfo,
-    LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx,
-    std::unique_ptr<MCRelocationInfo> &&RelInfo) {
+static MCSymbolizer *
+createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
+                                LLVMSymbolLookupCallback SymbolLookUp,
+                                void *DisInfo, MCContext *Ctx,
+                                std::unique_ptr<MCRelocationInfo> &&RelInfo) {
   return new llvm::AArch64ExternalSymbolizer(*Ctx, move(RelInfo), GetOpInfo,
                                              SymbolLookUp, DisInfo);
 }

Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp Tue Sep 15 11:17:27 2015
@@ -10,7 +10,7 @@
 #include "AArch64.h"
 #include "AArch64RegisterInfo.h"
 #include "MCTargetDesc/AArch64FixupKinds.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCDirectives.h"
 #include "llvm/MC/MCELFObjectWriter.h"
@@ -521,23 +521,23 @@ void ELFAArch64AsmBackend::applyFixup(co
 
 MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
                                               const MCRegisterInfo &MRI,
-                                              const TargetTuple &TT,
+                                              const Triple &TheTriple,
                                               StringRef CPU) {
-  if (TT.isOSBinFormatMachO())
+  if (TheTriple.isOSBinFormatMachO())
     return new DarwinAArch64AsmBackend(T, MRI);
 
-  assert(TT.isOSBinFormatELF() && "Expect either MachO or ELF target");
-  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
+  assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target");
+  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
   return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true);
 }
 
 MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
                                               const MCRegisterInfo &MRI,
-                                              const TargetTuple &TT,
+                                              const Triple &TheTriple,
                                               StringRef CPU) {
-  assert(TT.isOSBinFormatELF() &&
+  assert(TheTriple.isOSBinFormatELF() &&
          "Big endian is only supported for ELF targets!");
-  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
+  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
   return new ELFAArch64AsmBackend(T, OSABI,
                                   /*IsLittleEndian=*/false);
 }

Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp Tue Sep 15 11:17:27 2015
@@ -17,7 +17,6 @@
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/StringExtras.h"
-#include "llvm/ADT/TargetTuple.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAsmInfo.h"
@@ -199,7 +198,7 @@ MCELFStreamer *createAArch64ELFStreamer(
 
 MCTargetStreamer *
 createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
-  const TargetTuple &TT = STI.getTargetTuple();
+  const Triple &TT = STI.getTargetTriple();
   if (TT.isOSBinFormatELF())
     return new AArch64TargetELFStreamer(S);
   return nullptr;

Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "AArch64MCAsmInfo.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCStreamer.h"
@@ -69,8 +69,8 @@ const MCExpr *AArch64MCAsmInfoDarwin::ge
   return MCBinaryExpr::createSub(Res, PC, Context);
 }
 
-AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const TargetTuple &T) {
-  if (T.getArch() == TargetTuple::aarch64_be)
+AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const Triple &T) {
+  if (T.getArch() == Triple::aarch64_be)
     IsLittleEndian = false;
 
   // We prefer NEON instructions to be printed in the short form.

Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -20,7 +20,7 @@
 namespace llvm {
 class MCStreamer;
 class Target;
-class TargetTuple;
+class Triple;
 
 struct AArch64MCAsmInfoDarwin : public MCAsmInfoDarwin {
   explicit AArch64MCAsmInfoDarwin();
@@ -30,7 +30,7 @@ struct AArch64MCAsmInfoDarwin : public M
 };
 
 struct AArch64MCAsmInfoELF : public MCAsmInfoELF {
-  explicit AArch64MCAsmInfoELF(const TargetTuple &TT);
+  explicit AArch64MCAsmInfoELF(const Triple &T);
 };
 
 } // namespace llvm

Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -40,29 +40,28 @@ static MCInstrInfo *createAArch64MCInstr
   return X;
 }
 
-static MCSubtargetInfo *createAArch64MCSubtargetInfo(const TargetTuple &TT,
-                                                     StringRef CPU,
-                                                     StringRef FS) {
+static MCSubtargetInfo *
+createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   if (CPU.empty())
     CPU = "generic";
 
   return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCRegisterInfo *createAArch64MCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitAArch64MCRegisterInfo(X, AArch64::LR);
   return X;
 }
 
 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
-                                         const TargetTuple &TT) {
+                                         const Triple &TheTriple) {
   MCAsmInfo *MAI;
-  if (TT.isOSBinFormatMachO())
+  if (TheTriple.isOSBinFormatMachO())
     MAI = new AArch64MCAsmInfoDarwin();
   else {
-    assert(TT.isOSBinFormatELF() && "Only expect Darwin or ELF");
-    MAI = new AArch64MCAsmInfoELF(TT);
+    assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF");
+    MAI = new AArch64MCAsmInfoELF(TheTriple);
   }
 
   // Initial state of the frame pointer is SP.
@@ -73,7 +72,7 @@ static MCAsmInfo *createAArch64MCAsmInfo
   return MAI;
 }
 
-static MCCodeGenInfo *createAArch64MCCodeGenInfo(const TargetTuple &TT,
+static MCCodeGenInfo *createAArch64MCCodeGenInfo(const Triple &TT,
                                                  Reloc::Model RM,
                                                  CodeModel::Model CM,
                                                  CodeGenOpt::Level OL) {
@@ -105,7 +104,7 @@ static MCCodeGenInfo *createAArch64MCCod
   return X;
 }
 
-static MCInstPrinter *createAArch64MCInstPrinter(const TargetTuple &TT,
+static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,
@@ -118,7 +117,7 @@ static MCInstPrinter *createAArch64MCIns
   return nullptr;
 }
 
-static MCStreamer *createELFStreamer(const TargetTuple &TT, MCContext &Ctx,
+static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
                                      MCAsmBackend &TAB, raw_pwrite_stream &OS,
                                      MCCodeEmitter *Emitter, bool RelaxAll) {
   return createAArch64ELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);

Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h Tue Sep 15 11:17:27 2015
@@ -31,7 +31,7 @@ class MCSubtargetInfo;
 class MCTargetStreamer;
 class StringRef;
 class Target;
-class TargetTuple;
+class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
@@ -44,10 +44,10 @@ MCCodeEmitter *createAArch64MCCodeEmitte
                                           MCContext &Ctx);
 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const TargetTuple &TT, StringRef CPU);
+                                        const Triple &TT, StringRef CPU);
 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const TargetTuple &TT, StringRef CPU);
+                                        const Triple &TT, StringRef CPU);
 
 MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
                                              uint8_t OSABI,

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Tue Sep 15 11:17:27 2015
@@ -63,13 +63,13 @@ AMDGPUSubtarget::initializeSubtargetDepe
 
 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
                                  TargetMachine &TM)
-    : AMDGPUGenSubtargetInfo(TargetTuple(TT), GPU, FS), DevName(GPU),
-      Is64bit(false), DumpCode(false), R600ALUInst(false),
-      HasVertexCache(false), TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600),
-      FP64(false), FP64Denormals(false), FP32Denormals(false),
-      FastFMAF32(false), CaymanISA(false), FlatAddressSpace(false),
-      EnableIRStructurizer(true), EnablePromoteAlloca(false), EnableIfCvt(true),
-      EnableLoadStoreOpt(false), EnableUnsafeDSOffsetFolding(false),
+    : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
+      DumpCode(false), R600ALUInst(false), HasVertexCache(false),
+      TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
+      FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
+      CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true),
+      EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
+      EnableUnsafeDSOffsetFolding(false),
       WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
       EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
       GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),

Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp Tue Sep 15 11:17:27 2015
@@ -174,8 +174,9 @@ public:
 
 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
-                                           const TargetTuple &TT,
-                                           StringRef CPU) {
+                                           const Triple &TT, StringRef CPU) {
+  Triple TargetTriple(TT);
+
   // Use 64-bit ELF for amdgcn
-  return new ELFAMDGPUAsmBackend(T, TT.getArch() == TargetTuple::amdgcn);
+  return new ELFAMDGPUAsmBackend(T, TargetTriple.getArch() == Triple::amdgcn);
 }

Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -11,7 +11,7 @@
 #include "AMDGPUMCAsmInfo.h"
 
 using namespace llvm;
-AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const TargetTuple &TT) : MCAsmInfoELF() {
+AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT) : MCAsmInfoELF() {
   HasSingleParameterDotFile = false;
   //===------------------------------------------------------------------===//
   MaxInstLength = 16;

Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -17,7 +17,7 @@
 #include "llvm/MC/MCAsmInfoELF.h"
 namespace llvm {
 
-class TargetTuple;
+class Triple;
 
 // If you need to create another MCAsmInfo class, which inherits from MCAsmInfo,
 // you will need to make sure your new class sets PrivateGlobalPrefix to
@@ -26,7 +26,7 @@ class TargetTuple;
 // with 'L' as a local symbol.
 class AMDGPUMCAsmInfo : public MCAsmInfoELF {
 public:
-  explicit AMDGPUMCAsmInfo(const TargetTuple &TT);
+  explicit AMDGPUMCAsmInfo(const Triple &TT);
 };
 } // namespace llvm
 #endif

Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -44,19 +44,18 @@ static MCInstrInfo *createAMDGPUMCInstrI
   return X;
 }
 
-static MCRegisterInfo *createAMDGPUMCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitAMDGPUMCRegisterInfo(X, 0);
   return X;
 }
 
-static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(const TargetTuple &TT,
-                                                    StringRef CPU,
-                                                    StringRef FS) {
+static MCSubtargetInfo *
+createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const TargetTuple &TT,
+static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const Triple &TT,
                                                 Reloc::Model RM,
                                                 CodeModel::Model CM,
                                                 CodeGenOpt::Level OL) {
@@ -65,7 +64,7 @@ static MCCodeGenInfo *createAMDGPUMCCode
   return X;
 }
 
-static MCInstPrinter *createAMDGPUMCInstPrinter(const TargetTuple &T,
+static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
                                                 unsigned SyntaxVariant,
                                                 const MCAsmInfo &MAI,
                                                 const MCInstrInfo &MII,

Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h Tue Sep 15 11:17:27 2015
@@ -28,7 +28,7 @@ class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class Target;
-class TargetTuple;
+class Triple;
 class raw_pwrite_stream;
 class raw_ostream;
 
@@ -44,7 +44,7 @@ MCCodeEmitter *createSIMCCodeEmitter(con
                                      MCContext &Ctx);
 
 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                     const TargetTuple &TT, StringRef CPU);
+                                     const Triple &TT, StringRef CPU);
 
 MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
                                             raw_pwrite_stream &OS);

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Sep 15 11:17:27 2015
@@ -558,7 +558,7 @@ void ARMAsmPrinter::emitAttributes() {
   const Triple &TT = TM.getTargetTriple();
   StringRef CPU = TM.getTargetCPU();
   StringRef FS = TM.getTargetFeatureString();
-  std::string ArchFS = ARM_MC::ParseARMTargetTuple(TargetTuple(TT), CPU);
+  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Tue Sep 15 11:17:27 2015
@@ -81,7 +81,7 @@ ARMFrameLowering *ARMSubtarget::initiali
 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS,
                            const ARMBaseTargetMachine &TM, bool IsLittle)
-    : ARMGenSubtargetInfo(TargetTuple(TT), CPU, FS), ARMProcFamily(Others),
+    : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
       ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
       TargetTriple(TT), Options(TM.Options), TM(TM),
       FrameLowering(initializeFrameLowering(CPU, FS)),
@@ -159,8 +159,7 @@ void ARMSubtarget::initSubtargetFeatures
   // Insert the architecture feature derived from the target triple into the
   // feature string. This is important for setting features that are implied
   // based on the architecture version.
-  std::string ArchFS =
-      ARM_MC::ParseARMTargetTuple(TargetTuple(TargetTriple), CPUString);
+  std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Tue Sep 15 11:17:27 2015
@@ -779,49 +779,45 @@ static MachO::CPUSubTypeARM getMachOSubT
 
 MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const TargetTuple &TT, StringRef CPU,
+                                        const Triple &TheTriple, StringRef CPU,
                                         bool isLittle) {
-  switch (TT.getObjectFormat()) {
+  switch (TheTriple.getObjectFormat()) {
   default:
     llvm_unreachable("unsupported object format");
-  case TargetTuple::MachO: {
-    MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TT.getArchName());
-    return new ARMAsmBackendDarwin(T, TT, CS);
+  case Triple::MachO: {
+    MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());
+    return new ARMAsmBackendDarwin(T, TheTriple, CS);
   }
-  case TargetTuple::COFF:
-    assert(TT.isOSWindows() && "non-Windows ARM COFF is not supported");
-    return new ARMAsmBackendWinCOFF(T, TT);
-  case TargetTuple::ELF:
-    assert(TT.isOSBinFormatELF() && "using ELF for non-ELF target");
-    uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
-    return new ARMAsmBackendELF(T, TT, OSABI, isLittle);
+  case Triple::COFF:
+    assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
+    return new ARMAsmBackendWinCOFF(T, TheTriple);
+  case Triple::ELF:
+    assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
+    uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
+    return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle);
   }
 }
 
 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          const TargetTuple &TT,
-                                          StringRef CPU) {
+                                          const Triple &TT, StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, true);
 }
 
 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          const TargetTuple &TT,
-                                          StringRef CPU) {
+                                          const Triple &TT, StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, false);
 }
 
 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
                                             const MCRegisterInfo &MRI,
-                                            const TargetTuple &TT,
-                                            StringRef CPU) {
+                                            const Triple &TT, StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, true);
 }
 
 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
                                             const MCRegisterInfo &MRI,
-                                            const TargetTuple &TT,
-                                            StringRef CPU) {
+                                            const Triple &TT, StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, false);
 }

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h Tue Sep 15 11:17:27 2015
@@ -23,7 +23,7 @@ class ARMAsmBackend : public MCAsmBacken
   bool isThumbMode;    // Currently emitting Thumb code.
   bool IsLittleEndian; // Big or little endian.
 public:
-  ARMAsmBackend(const Target &T, const TargetTuple &TT, bool IsLittle)
+  ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle)
       : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
         isThumbMode(TT.getArchName().startswith("thumb")),
         IsLittleEndian(IsLittle) {}

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h Tue Sep 15 11:17:27 2015
@@ -18,7 +18,7 @@ namespace {
 class ARMAsmBackendDarwin : public ARMAsmBackend {
 public:
   const MachO::CPUSubTypeARM Subtype;
-  ARMAsmBackendDarwin(const Target &T, const TargetTuple &TT,
+  ARMAsmBackendDarwin(const Target &T, const Triple &TT,
                       MachO::CPUSubTypeARM st)
       : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) {
     HasDataInCodeSupport = true;

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h Tue Sep 15 11:17:27 2015
@@ -15,7 +15,7 @@ namespace {
 class ARMAsmBackendELF : public ARMAsmBackend {
 public:
   uint8_t OSABI;
-  ARMAsmBackendELF(const Target &T, const TargetTuple &TT, uint8_t OSABI,
+  ARMAsmBackendELF(const Target &T, const Triple &TT, uint8_t OSABI,
                    bool IsLittle)
       : ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {}
 

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h Tue Sep 15 11:17:27 2015
@@ -15,8 +15,8 @@ using namespace llvm;
 namespace {
 class ARMAsmBackendWinCOFF : public ARMAsmBackend {
 public:
-  ARMAsmBackendWinCOFF(const Target &T, const TargetTuple &TT)
-      : ARMAsmBackend(T, TT, true) {}
+  ARMAsmBackendWinCOFF(const Target &T, const Triple &TheTriple)
+      : ARMAsmBackend(T, TheTriple, true) {}
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false);
   }

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp Tue Sep 15 11:17:27 2015
@@ -1361,7 +1361,7 @@ MCTargetStreamer *createARMNullTargetStr
 
 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
                                                 const MCSubtargetInfo &STI) {
-  const TargetTuple &TT = STI.getTargetTuple();
+  const Triple &TT = STI.getTargetTriple();
   if (TT.isOSBinFormatELF())
     return new ARMTargetELFStreamer(S);
   return new ARMTargetStreamer(S);

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -12,16 +12,16 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARMMCAsmInfo.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
 void ARMMCAsmInfoDarwin::anchor() { }
 
-ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const TargetTuple &TT) {
-  if ((TT.getArch() == TargetTuple::armeb) ||
-      (TT.getArch() == TargetTuple::thumbeb))
+ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) {
+  if ((TheTriple.getArch() == Triple::armeb) ||
+      (TheTriple.getArch() == Triple::thumbeb))
     IsLittleEndian = false;
 
   Data64bitsDirective = nullptr;
@@ -40,9 +40,9 @@ ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(c
 
 void ARMELFMCAsmInfo::anchor() { }
 
-ARMELFMCAsmInfo::ARMELFMCAsmInfo(const TargetTuple &TT) {
-  if ((TT.getArch() == TargetTuple::armeb) ||
-      (TT.getArch() == TargetTuple::thumbeb))
+ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) {
+  if ((TheTriple.getArch() == Triple::armeb) ||
+      (TheTriple.getArch() == Triple::thumbeb))
     IsLittleEndian = false;
 
   // ".comm align is in bytes but .align is pow-2."
@@ -56,9 +56,9 @@ ARMELFMCAsmInfo::ARMELFMCAsmInfo(const T
   SupportsDebugInformation = true;
 
   // Exceptions handling
-  switch (TT.getOS()) {
-  case TargetTuple::Bitrig:
-  case TargetTuple::NetBSD:
+  switch (TheTriple.getOS()) {
+  case Triple::Bitrig:
+  case Triple::NetBSD:
     ExceptionsType = ExceptionHandling::DwarfCFI;
     break;
   default:

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -19,20 +19,20 @@
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class TargetTuple;
+class Triple;
 
 class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit ARMMCAsmInfoDarwin(const TargetTuple &TT);
+  explicit ARMMCAsmInfoDarwin(const Triple &TheTriple);
 };
 
 class ARMELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit ARMELFMCAsmInfo(const TargetTuple &TT);
+  explicit ARMELFMCAsmInfo(const Triple &TT);
 
   void setUseIntegratedAssembler(bool Value) override;
 };

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Tue Sep 15 11:17:27 2015
@@ -57,7 +57,7 @@ public:
     return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
   }
   bool isTargetMachO(const MCSubtargetInfo &STI) const {
-    const TargetTuple &TT = STI.getTargetTuple();
+    const Triple &TT = STI.getTargetTriple();
     return TT.isOSBinFormatMachO();
   }
 

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -15,7 +15,7 @@
 #include "ARMMCAsmInfo.h"
 #include "ARMMCTargetDesc.h"
 #include "InstPrinter/ARMInstPrinter.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrAnalysis.h"
@@ -130,16 +130,16 @@ static bool getARMLoadDeprecationInfo(MC
 #define GET_SUBTARGETINFO_MC_DESC
 #include "ARMGenSubtargetInfo.inc"
 
-std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) {
-  bool isThumb = TT.getArch() == TargetTuple::thumb ||
-                 TT.getArch() == TargetTuple::thumbeb;
+std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
+  bool isThumb =
+      TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
 
   bool NoCPU = CPU == "generic" || CPU.empty();
   std::string ARMArchFeature;
   switch (TT.getSubArch()) {
   default:
     llvm_unreachable("invalid sub-architecture for ARM");
-  case TargetTuple::ARMSubArch_v8:
+  case Triple::ARMSubArch_v8:
     if (NoCPU)
       // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
@@ -150,7 +150,7 @@ std::string ARM_MC::ParseARMTargetTuple(
       // Use CPU to figure out the exact features
       ARMArchFeature = "+v8";
     break;
-  case TargetTuple::ARMSubArch_v8_1a:
+  case Triple::ARMSubArch_v8_1a:
     if (NoCPU)
       // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
@@ -161,7 +161,7 @@ std::string ARM_MC::ParseARMTargetTuple(
       // Use CPU to figure out the exact features
       ARMArchFeature = "+v8.1a";
     break;
-  case TargetTuple::ARMSubArch_v7m:
+  case Triple::ARMSubArch_v7m:
     isThumb = true;
     if (NoCPU)
       // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
@@ -170,7 +170,7 @@ std::string ARM_MC::ParseARMTargetTuple(
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case TargetTuple::ARMSubArch_v7em:
+  case Triple::ARMSubArch_v7em:
     if (NoCPU)
       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
       //       FeatureT2XtPk, FeatureMClass
@@ -179,7 +179,7 @@ std::string ARM_MC::ParseARMTargetTuple(
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case TargetTuple::ARMSubArch_v7s:
+  case Triple::ARMSubArch_v7s:
     if (NoCPU)
       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
       //      Swift
@@ -188,7 +188,7 @@ std::string ARM_MC::ParseARMTargetTuple(
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case TargetTuple::ARMSubArch_v7:
+  case Triple::ARMSubArch_v7:
     // v7 CPUs have lots of different feature sets. If no CPU is specified,
     // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
     // the "minimum" feature set and use CPU string to figure out the exact
@@ -200,13 +200,13 @@ std::string ARM_MC::ParseARMTargetTuple(
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case TargetTuple::ARMSubArch_v6t2:
+  case Triple::ARMSubArch_v6t2:
     ARMArchFeature = "+v6t2";
     break;
-  case TargetTuple::ARMSubArch_v6k:
+  case Triple::ARMSubArch_v6k:
     ARMArchFeature = "+v6k";
     break;
-  case TargetTuple::ARMSubArch_v6m:
+  case Triple::ARMSubArch_v6m:
     isThumb = true;
     if (NoCPU)
       // v6m: FeatureNoARM, FeatureMClass
@@ -214,19 +214,19 @@ std::string ARM_MC::ParseARMTargetTuple(
     else
       ARMArchFeature = "+v6";
     break;
-  case TargetTuple::ARMSubArch_v6:
+  case Triple::ARMSubArch_v6:
     ARMArchFeature = "+v6";
     break;
-  case TargetTuple::ARMSubArch_v5te:
+  case Triple::ARMSubArch_v5te:
     ARMArchFeature = "+v5te";
     break;
-  case TargetTuple::ARMSubArch_v5:
+  case Triple::ARMSubArch_v5:
     ARMArchFeature = "+v5t";
     break;
-  case TargetTuple::ARMSubArch_v4t:
+  case Triple::ARMSubArch_v4t:
     ARMArchFeature = "+v4t";
     break;
-  case TargetTuple::NoSubArch:
+  case Triple::NoSubArch:
     break;
   }
 
@@ -247,9 +247,9 @@ std::string ARM_MC::ParseARMTargetTuple(
   return ARMArchFeature;
 }
 
-MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const TargetTuple &TT,
+MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
                                                   StringRef CPU, StringRef FS) {
-  std::string ArchFS = ARM_MC::ParseARMTargetTuple(TT, CPU);
+  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
@@ -266,23 +266,23 @@ static MCInstrInfo *createARMMCInstrInfo
   return X;
 }
 
-static MCRegisterInfo *createARMMCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
   return X;
 }
 
 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
-                                     const TargetTuple &TT) {
+                                     const Triple &TheTriple) {
   MCAsmInfo *MAI;
-  if (TT.isOSDarwin() || TT.isOSBinFormatMachO())
-    MAI = new ARMMCAsmInfoDarwin(TT);
-  else if (TT.isWindowsMSVCEnvironment())
+  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
+    MAI = new ARMMCAsmInfoDarwin(TheTriple);
+  else if (TheTriple.isWindowsMSVCEnvironment())
     MAI = new ARMCOFFMCAsmInfoMicrosoft();
-  else if (TT.isOSWindows())
+  else if (TheTriple.isOSWindows())
     MAI = new ARMCOFFMCAsmInfoGNU();
   else
-    MAI = new ARMELFMCAsmInfo(TT);
+    MAI = new ARMELFMCAsmInfo(TheTriple);
 
   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
@@ -290,8 +290,7 @@ static MCAsmInfo *createARMMCAsmInfo(con
   return MAI;
 }
 
-static MCCodeGenInfo *createARMMCCodeGenInfo(const TargetTuple &TT,
-                                             Reloc::Model RM,
+static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
@@ -303,11 +302,11 @@ static MCCodeGenInfo *createARMMCCodeGen
   return X;
 }
 
-static MCStreamer *createELFStreamer(const TargetTuple &TT, MCContext &Ctx,
+static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
                                      MCAsmBackend &MAB, raw_pwrite_stream &OS,
                                      MCCodeEmitter *Emitter, bool RelaxAll) {
   return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
-                              TT.getArch() == TargetTuple::thumb);
+                              T.getArch() == Triple::thumb);
 }
 
 static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB,
@@ -317,7 +316,7 @@ static MCStreamer *createARMMachOStreame
   return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd);
 }
 
-static MCInstPrinter *createARMMCInstPrinter(const TargetTuple &TT,
+static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
                                              unsigned SyntaxVariant,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,
@@ -327,7 +326,7 @@ static MCInstPrinter *createARMMCInstPri
   return nullptr;
 }
 
-static MCRelocationInfo *createARMMCRelocationInfo(const TargetTuple &TT,
+static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
                                                    MCContext &Ctx) {
   if (TT.isOSBinFormatMachO())
     return createARMMachORelocationInfo(Ctx);

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Tue Sep 15 11:17:27 2015
@@ -32,7 +32,7 @@ class MCRelocationInfo;
 class MCTargetStreamer;
 class StringRef;
 class Target;
-class TargetTuple;
+class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
@@ -40,11 +40,11 @@ extern Target TheARMLETarget, TheThumbLE
 extern Target TheARMBETarget, TheThumbBETarget;
 
 namespace ARM_MC {
-std::string ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU);
+std::string ParseARMTriple(const Triple &TT, StringRef CPU);
 
 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
-MCSubtargetInfo *createARMMCSubtargetInfo(const TargetTuple &TT, StringRef CPU,
+MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
@@ -65,22 +65,22 @@ MCCodeEmitter *createARMBEMCCodeEmitter(
                                         MCContext &Ctx);
 
 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  const TargetTuple &TT, StringRef CPU,
+                                  const Triple &TT, StringRef CPU,
                                   bool IsLittleEndian);
 
 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const TargetTuple &TT, StringRef CPU);
+                                    const Triple &TT, StringRef CPU);
 
 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const TargetTuple &TT, StringRef CPU);
+                                    const Triple &TT, StringRef CPU);
 
 MCAsmBackend *createThumbLEAsmBackend(const Target &T,
                                       const MCRegisterInfo &MRI,
-                                      const TargetTuple &TT, StringRef CPU);
+                                      const Triple &TT, StringRef CPU);
 
 MCAsmBackend *createThumbBEAsmBackend(const Target &T,
                                       const MCRegisterInfo &MRI,
-                                      const TargetTuple &TT, StringRef CPU);
+                                      const Triple &TT, StringRef CPU);
 
 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
 // object file.

Modified: llvm/trunk/lib/Target/BPF/BPFSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/BPFSubtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/BPFSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/BPF/BPFSubtarget.cpp Tue Sep 15 11:17:27 2015
@@ -27,5 +27,5 @@ void BPFSubtarget::anchor() {}
 
 BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const TargetMachine &TM)
-    : BPFGenSubtargetInfo(TargetTuple(TT), CPU, FS), InstrInfo(),
-      FrameLowering(*this), TLInfo(TM, *this) {}
+    : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
+      TLInfo(TM, *this) {}

Modified: llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp Tue Sep 15 11:17:27 2015
@@ -95,13 +95,12 @@ MCObjectWriter *BPFAsmBackend::createObj
 
 MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const TargetTuple &TT, StringRef CPU) {
+                                        const Triple &TT, StringRef CPU) {
   return new BPFAsmBackend(/*IsLittleEndian=*/true);
 }
 
 MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          const TargetTuple &TT,
-                                          StringRef CPU) {
+                                          const Triple &TT, StringRef CPU) {
   return new BPFAsmBackend(/*IsLittleEndian=*/false);
 }

Modified: llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -16,15 +16,16 @@
 
 #include "llvm/ADT/StringRef.h"
 #include "llvm/MC/MCAsmInfo.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 
 namespace llvm {
 class Target;
+class Triple;
 
 class BPFMCAsmInfo : public MCAsmInfo {
 public:
-  explicit BPFMCAsmInfo(const TargetTuple &TT) {
-    if (TT.getArch() == TargetTuple::bpfeb)
+  explicit BPFMCAsmInfo(const Triple &TT) {
+    if (TT.getArch() == Triple::bpfeb)
       IsLittleEndian = false;
 
     PrivateGlobalPrefix = ".L";

Modified: llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -40,19 +40,18 @@ static MCInstrInfo *createBPFMCInstrInfo
   return X;
 }
 
-static MCRegisterInfo *createBPFMCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createBPFMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */);
   return X;
 }
 
-static MCSubtargetInfo *createBPFMCSubtargetInfo(const TargetTuple &TT,
+static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT,
                                                  StringRef CPU, StringRef FS) {
   return createBPFMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCCodeGenInfo *createBPFMCCodeGenInfo(const TargetTuple &TT,
-                                             Reloc::Model RM,
+static MCCodeGenInfo *createBPFMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
@@ -60,13 +59,14 @@ static MCCodeGenInfo *createBPFMCCodeGen
   return X;
 }
 
-static MCStreamer *createBPFMCStreamer(const TargetTuple &TT, MCContext &Ctx,
-                                       MCAsmBackend &MAB, raw_pwrite_stream &OS,
-                                       MCCodeEmitter *Emitter, bool RelaxAll) {
+static MCStreamer *createBPFMCStreamer(const Triple &T,
+                                       MCContext &Ctx, MCAsmBackend &MAB,
+                                       raw_pwrite_stream &OS, MCCodeEmitter *Emitter,
+                                       bool RelaxAll) {
   return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
 }
 
-static MCInstPrinter *createBPFMCInstPrinter(const TargetTuple &TT,
+static MCInstPrinter *createBPFMCInstPrinter(const Triple &T,
                                              unsigned SyntaxVariant,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,

Modified: llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h Tue Sep 15 11:17:27 2015
@@ -27,7 +27,7 @@ class MCRegisterInfo;
 class MCSubtargetInfo;
 class StringRef;
 class Target;
-class TargetTuple;
+class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
@@ -43,9 +43,9 @@ MCCodeEmitter *createBPFbeMCCodeEmitter(
                                         MCContext &Ctx);
 
 MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  const TargetTuple &TT, StringRef CPU);
+                                  const Triple &TT, StringRef CPU);
 MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const TargetTuple &TT, StringRef CPU);
+                                    const Triple &TT, StringRef CPU);
 
 MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS,
                                          uint8_t OSABI, bool IsLittleEndian);

Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Tue Sep 15 11:17:27 2015
@@ -72,7 +72,7 @@ HexagonSubtarget::initializeSubtargetDep
 
 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
                                    StringRef FS, const TargetMachine &TM)
-    : HexagonGenSubtargetInfo(TargetTuple(TT), CPU, FS), CPUString(CPU),
+    : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       FrameLowering() {
 

Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp Tue Sep 15 11:17:27 2015
@@ -309,7 +309,7 @@ public:
 namespace llvm {
 MCAsmBackend *createHexagonAsmBackend(Target const &T,
                                       MCRegisterInfo const & /*MRI*/,
-                                      const TargetTuple &TT, StringRef CPU) {
+                                      const Triple &TT, StringRef CPU) {
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
   return new HexagonAsmBackend(T, OSABI, CPU);
 }

Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -18,7 +18,7 @@ using namespace llvm;
 // Pin the vtable to this file.
 void HexagonMCAsmInfo::anchor() {}
 
-HexagonMCAsmInfo::HexagonMCAsmInfo(const TargetTuple &TT) {
+HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) {
   Data16bitsDirective = "\t.half\t";
   Data32bitsDirective = "\t.word\t";
   Data64bitsDirective = nullptr;  // .xword is only supported by V9.

Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -18,13 +18,13 @@
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class TargetTuple;
+class Triple;
 
 class HexagonMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit HexagonMCAsmInfo(const TargetTuple &TT);
+  explicit HexagonMCAsmInfo(const Triple &TT);
 };
 
 } // namespace llvm

Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -46,15 +46,14 @@ MCInstrInfo *llvm::createHexagonMCInstrI
   return X;
 }
 
-static MCRegisterInfo *createHexagonMCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitHexagonMCRegisterInfo(X, Hexagon::R0);
   return X;
 }
 
-static MCSubtargetInfo *createHexagonMCSubtargetInfo(const TargetTuple &TT,
-                                                     StringRef CPU,
-                                                     StringRef FS) {
+static MCSubtargetInfo *
+createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
@@ -139,7 +138,7 @@ public:
 }
 
 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
-                                         const TargetTuple &TT) {
+                                         const Triple &TT) {
   MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
 
   // VirtualFP = (R30 + #0).
@@ -150,7 +149,7 @@ static MCAsmInfo *createHexagonMCAsmInfo
   return MAI;
 }
 
-static MCCodeGenInfo *createHexagonMCCodeGenInfo(const TargetTuple &TT,
+static MCCodeGenInfo *createHexagonMCCodeGenInfo(const Triple &TT,
                                                  Reloc::Model RM,
                                                  CodeModel::Model CM,
                                                  CodeGenOpt::Level OL) {
@@ -161,7 +160,7 @@ static MCCodeGenInfo *createHexagonMCCod
   return X;
 }
 
-static MCInstPrinter *createHexagonMCInstPrinter(const TargetTuple &TT,
+static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,
@@ -179,7 +178,7 @@ static MCTargetStreamer *createMCAsmTarg
   return new HexagonTargetAsmStreamer(S,  OS, IsVerboseAsm, *InstPrint);
 }
 
-static MCStreamer *createMCStreamer(const TargetTuple &TT, MCContext &Context,
+static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
                                     MCCodeEmitter *Emitter, bool RelaxAll) {
   return createHexagonELFStreamer(Context, MAB, OS, Emitter);

Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h Tue Sep 15 11:17:27 2015
@@ -27,7 +27,7 @@ class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class Target;
-class TargetTuple;
+class Triple;
 class StringRef;
 class raw_ostream;
 class raw_pwrite_stream;
@@ -44,7 +44,7 @@ MCCodeEmitter *createHexagonMCCodeEmitte
 
 MCAsmBackend *createHexagonAsmBackend(Target const &T,
                                       MCRegisterInfo const &MRI,
-                                      const TargetTuple &TT, StringRef CPU);
+                                      const Triple &TT, StringRef CPU);
 
 MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
                                              uint8_t OSABI, StringRef CPU);

Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -16,7 +16,7 @@ using namespace llvm;
 
 void MSP430MCAsmInfo::anchor() { }
 
-MSP430MCAsmInfo::MSP430MCAsmInfo(const TargetTuple &TT) {
+MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) {
   PointerSize = CalleeSaveStackSlotSize = 2;
 
   CommentString = ";";

Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -17,13 +17,13 @@
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class TargetTuple;
+class Triple;
 
 class MSP430MCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit MSP430MCAsmInfo(const TargetTuple &TT);
+  explicit MSP430MCAsmInfo(const Triple &TT);
 };
 
 } // namespace llvm

Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -37,19 +37,18 @@ static MCInstrInfo *createMSP430MCInstrI
   return X;
 }
 
-static MCRegisterInfo *createMSP430MCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createMSP430MCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitMSP430MCRegisterInfo(X, MSP430::PC);
   return X;
 }
 
-static MCSubtargetInfo *createMSP430MCSubtargetInfo(const TargetTuple &TT,
-                                                    StringRef CPU,
-                                                    StringRef FS) {
+static MCSubtargetInfo *
+createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   return createMSP430MCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCCodeGenInfo *createMSP430MCCodeGenInfo(const TargetTuple &TT,
+static MCCodeGenInfo *createMSP430MCCodeGenInfo(const Triple &TT,
                                                 Reloc::Model RM,
                                                 CodeModel::Model CM,
                                                 CodeGenOpt::Level OL) {
@@ -58,7 +57,7 @@ static MCCodeGenInfo *createMSP430MCCode
   return X;
 }
 
-static MCInstPrinter *createMSP430MCInstPrinter(const TargetTuple &T,
+static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T,
                                                 unsigned SyntaxVariant,
                                                 const MCAsmInfo &MAI,
                                                 const MCInstrInfo &MII,

Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Tue Sep 15 11:17:27 2015
@@ -33,5 +33,5 @@ MSP430Subtarget::initializeSubtargetDepe
 
 MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,
                                  const std::string &FS, const TargetMachine &TM)
-    : MSP430GenSubtargetInfo(TargetTuple(TT), CPU, FS), FrameLowering(),
+    : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {}

Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Tue Sep 15 11:17:27 2015
@@ -375,8 +375,8 @@ public:
   MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
                 const MCInstrInfo &MII, const MCTargetOptions &Options)
       : MCTargetAsmParser(Options), STI(sti),
-        ABI(MipsABIInfo::computeTargetABI(sti.getTargetTuple(), sti.getCPU(),
-                                          Options)) {
+        ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
+                                          sti.getCPU(), Options)) {
     MCAsmParserExtension::Initialize(parser);
 
     parser.addAliasForDirective(".asciiz", ".asciz");
@@ -402,9 +402,9 @@ public:
     IsPicEnabled =
         (getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_);
 
-    const TargetTuple &TT = sti.getTargetTuple();
-    if ((TT.getArch() == TargetTuple::mips) ||
-        (TT.getArch() == TargetTuple::mips64))
+    Triple TheTriple(sti.getTargetTriple());
+    if ((TheTriple.getArch() == Triple::mips) ||
+        (TheTriple.getArch() == Triple::mips64))
       IsLittleEndian = false;
     else
       IsLittleEndian = true;

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp Tue Sep 15 11:17:27 2015
@@ -47,7 +47,7 @@ unsigned MipsABIInfo::GetCalleeAllocdArg
   llvm_unreachable("Unhandled ABI");
 }
 
-MipsABIInfo MipsABIInfo::computeTargetABI(const TargetTuple &TT, StringRef CPU,
+MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
                                           const MCTargetOptions &Options) {
   if (Options.getABIName().startswith("o32"))
     return MipsABIInfo::O32();
@@ -64,8 +64,7 @@ MipsABIInfo MipsABIInfo::computeTargetAB
   // used and not shared in a couple of other places. This needs unifying
   // at some level.
   if (CPU.empty() || CPU == "generic") {
-    if (TT.getArch() == TargetTuple::mips ||
-        TT.getArch() == TargetTuple::mipsel)
+    if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
       CPU = "mips32";
     else
       CPU = "mips64";

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h Tue Sep 15 11:17:27 2015
@@ -11,7 +11,7 @@
 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H
 
 #include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/MC/MCRegisterInfo.h"
 
@@ -36,7 +36,7 @@ public:
   static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); }
   static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); }
   static MipsABIInfo EABI() { return MipsABIInfo(ABI::EABI); }
-  static MipsABIInfo computeTargetABI(const TargetTuple &TT, StringRef CPU,
+  static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU,
                                       const MCTargetOptions &Options);
 
   bool IsKnown() const { return ThisABI != ABI::Unknown; }

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Tue Sep 15 11:17:27 2015
@@ -411,31 +411,27 @@ void MipsAsmBackend::processFixupValue(c
 // MCAsmBackend
 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
                                              const MCRegisterInfo &MRI,
-                                             const TargetTuple &TT,
-                                             StringRef CPU) {
+                                             const Triple &TT, StringRef CPU) {
   return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
                             /*Is64Bit*/ false);
 }
 
 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
                                              const MCRegisterInfo &MRI,
-                                             const TargetTuple &TT,
-                                             StringRef CPU) {
+                                             const Triple &TT, StringRef CPU) {
   return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
                             /*Is64Bit*/ false);
 }
 
 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
                                              const MCRegisterInfo &MRI,
-                                             const TargetTuple &TT,
-                                             StringRef CPU) {
+                                             const Triple &TT, StringRef CPU) {
   return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
 }
 
 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
                                              const MCRegisterInfo &MRI,
-                                             const TargetTuple &TT,
-                                             StringRef CPU) {
+                                             const Triple &TT, StringRef CPU) {
   return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
                             /*Is64Bit*/ true);
 }

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Tue Sep 15 11:17:27 2015
@@ -16,7 +16,7 @@
 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
 
 #include "MCTargetDesc/MipsFixupKinds.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCAsmBackend.h"
 
 namespace llvm {
@@ -27,12 +27,12 @@ class Target;
 class MCObjectWriter;
 
 class MipsAsmBackend : public MCAsmBackend {
-  TargetTuple::OSType OSType;
+  Triple::OSType OSType;
   bool IsLittle; // Big or little endian
   bool Is64Bit;  // 32 or 64 bit words
 
 public:
-  MipsAsmBackend(const Target &T, TargetTuple::OSType OSType, bool IsLittle,
+  MipsAsmBackend(const Target &T, Triple::OSType OSType, bool IsLittle,
                  bool Is64Bit)
       : MCAsmBackend(), OSType(OSType), IsLittle(IsLittle), Is64Bit(Is64Bit) {}
 

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -12,19 +12,19 @@
 //===----------------------------------------------------------------------===//
 
 #include "MipsMCAsmInfo.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 
 using namespace llvm;
 
 void MipsMCAsmInfo::anchor() { }
 
-MipsMCAsmInfo::MipsMCAsmInfo(const TargetTuple &TT) {
-  if ((TT.getArch() == TargetTuple::mips) ||
-      (TT.getArch() == TargetTuple::mips64))
+MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) {
+  if ((TheTriple.getArch() == Triple::mips) ||
+      (TheTriple.getArch() == Triple::mips64))
     IsLittleEndian = false;
 
-  if ((TT.getArch() == TargetTuple::mips64el) ||
-      (TT.getArch() == TargetTuple::mips64)) {
+  if ((TheTriple.getArch() == Triple::mips64el) ||
+      (TheTriple.getArch() == Triple::mips64)) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
 

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -17,13 +17,13 @@
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class TargetTuple;
+class Triple;
 
 class MipsMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit MipsMCAsmInfo(const TargetTuple &TT);
+  explicit MipsMCAsmInfo(const Triple &TheTriple);
 };
 
 } // namespace llvm

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -17,7 +17,7 @@
 #include "MipsMCNaCl.h"
 #include "MipsMCTargetDesc.h"
 #include "MipsTargetStreamer.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrInfo.h"
@@ -43,10 +43,9 @@ using namespace llvm;
 
 /// Select the Mips CPU for the given triple and cpu name.
 /// FIXME: Merge with the copy in MipsSubtarget.cpp
-StringRef MIPS_MC::selectMipsCPU(const TargetTuple &TT, StringRef CPU) {
+StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
   if (CPU.empty() || CPU == "generic") {
-    if (TT.getArch() == TargetTuple::mips ||
-        TT.getArch() == TargetTuple::mipsel)
+    if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
       CPU = "mips32";
     else
       CPU = "mips64";
@@ -60,20 +59,20 @@ static MCInstrInfo *createMipsMCInstrInf
   return X;
 }
 
-static MCRegisterInfo *createMipsMCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitMipsMCRegisterInfo(X, Mips::RA);
   return X;
 }
 
-static MCSubtargetInfo *createMipsMCSubtargetInfo(const TargetTuple &TT,
+static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
                                                   StringRef CPU, StringRef FS) {
   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
   return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
-                                      const TargetTuple &TT) {
+                                      const Triple &TT) {
   MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
 
   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
@@ -83,8 +82,7 @@ static MCAsmInfo *createMipsMCAsmInfo(co
   return MAI;
 }
 
-static MCCodeGenInfo *createMipsMCCodeGenInfo(const TargetTuple &TT,
-                                              Reloc::Model RM,
+static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
                                               CodeModel::Model CM,
                                               CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
@@ -96,7 +94,7 @@ static MCCodeGenInfo *createMipsMCCodeGe
   return X;
 }
 
-static MCInstPrinter *createMipsMCInstPrinter(const TargetTuple &T,
+static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
                                               unsigned SyntaxVariant,
                                               const MCAsmInfo &MAI,
                                               const MCInstrInfo &MII,
@@ -104,7 +102,7 @@ static MCInstPrinter *createMipsMCInstPr
   return new MipsInstPrinter(MAI, MII, MRI);
 }
 
-static MCStreamer *createMCStreamer(const TargetTuple &T, MCContext &Context,
+static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
                                     MCCodeEmitter *Emitter, bool RelaxAll) {
   MCStreamer *S;

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h Tue Sep 15 11:17:27 2015
@@ -26,7 +26,7 @@ class MCRegisterInfo;
 class MCSubtargetInfo;
 class StringRef;
 class Target;
-class TargetTuple;
+class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
@@ -44,22 +44,22 @@ MCCodeEmitter *createMipsMCCodeEmitterEL
 
 MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
                                        const MCRegisterInfo &MRI,
-                                       const TargetTuple &TT, StringRef CPU);
+                                       const Triple &TT, StringRef CPU);
 MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
                                        const MCRegisterInfo &MRI,
-                                       const TargetTuple &TT, StringRef CPU);
+                                       const Triple &TT, StringRef CPU);
 MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
                                        const MCRegisterInfo &MRI,
-                                       const TargetTuple &TT, StringRef CPU);
+                                       const Triple &TT, StringRef CPU);
 MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
                                        const MCRegisterInfo &MRI,
-                                       const TargetTuple &TT, StringRef CPU);
+                                       const Triple &TT, StringRef CPU);
 
 MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
                                           bool IsLittleEndian, bool Is64Bit);
 
 namespace MIPS_MC {
-StringRef selectMipsCPU(const TargetTuple &TT, StringRef CPU);
+StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
 }
 
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Tue Sep 15 11:17:27 2015
@@ -693,12 +693,11 @@ void MipsAsmPrinter::EmitStartOfAsmFile(
   // clean anyhow.
   // FIXME: For ifunc related functions we could iterate over and look
   // for a feature string that doesn't match the default one.
-  TargetTuple TT(TargetTuple(TM.getTargetTriple()));
+  const Triple &TT = TM.getTargetTriple();
   StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
   StringRef FS = TM.getTargetFeatureString();
   const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
-  const MipsSubtarget STI(TM.getTargetTriple(), CPU, FS, MTM.isLittleEndian(),
-                          MTM);
+  const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);
 
   bool IsABICalls = STI.isABICalls();
   const MipsABIInfo &ABI = MTM.getABI();

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Tue Sep 15 11:17:27 2015
@@ -62,16 +62,16 @@ void MipsSubtarget::anchor() { }
 MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
                              const std::string &FS, bool little,
                              const MipsTargetMachine &TM)
-    : MipsGenSubtargetInfo(TargetTuple(TT), CPU, FS),
-      MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false),
-      IsSingleFloat(false), IsFPXX(false), NoABICalls(false), IsFP64bit(false),
-      UseOddSPReg(true), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
-      HasCnMips(false), HasMips3_32(false), HasMips3_32r2(false),
-      HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
-      InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
-      InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
-      AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
-      UseTCCInDIV(false), HasEVA(false), TM(TM), TargetTriple(TT), TSInfo(),
+    : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
+      IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
+      NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
+      IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
+      HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
+      HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
+      InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
+      HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
+      HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM),
+      TargetTriple(TT), TSInfo(),
       InstrInfo(
           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
       FrameLowering(MipsFrameLowering::create(*this)),
@@ -142,8 +142,7 @@ CodeGenOpt::Level MipsSubtarget::getOptL
 MipsSubtarget &
 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
                                                const TargetMachine &TM) {
-  std::string CPUName =
-      MIPS_MC::selectMipsCPU(TargetTuple(TM.getTargetTriple()), CPU);
+  std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Tue Sep 15 11:17:27 2015
@@ -48,8 +48,7 @@ static std::string computeDataLayout(con
                                      const TargetOptions &Options,
                                      bool isLittle) {
   std::string Ret = "";
-  MipsABIInfo ABI =
-      MipsABIInfo::computeTargetABI(TargetTuple(TT), CPU, Options.MCOptions);
+  MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
 
   // There are both little and big endian mips.
   if (isLittle)
@@ -91,8 +90,7 @@ MipsTargetMachine::MipsTargetMachine(con
     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
                         CPU, FS, Options, RM, CM, OL),
       isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
-      ABI(MipsABIInfo::computeTargetABI(TargetTuple(TT), CPU,
-                                        Options.MCOptions)),
+      ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
       Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
       NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
                         isLittle, *this),

Modified: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "NVPTXMCAsmInfo.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
@@ -25,8 +25,8 @@ static cl::opt<bool> CompileForDebugging
 
 void NVPTXMCAsmInfo::anchor() {}
 
-NVPTXMCAsmInfo::NVPTXMCAsmInfo(const TargetTuple &TT) {
-  if (TT.getArch() == TargetTuple::nvptx64) {
+NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Triple &TheTriple) {
+  if (TheTriple.getArch() == Triple::nvptx64) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
 

Modified: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -18,13 +18,13 @@
 
 namespace llvm {
 class Target;
-class TargetTuple;
+class Triple;
 
 class NVPTXMCAsmInfo : public MCAsmInfo {
   virtual void anchor();
 
 public:
-  explicit NVPTXMCAsmInfo(const TargetTuple &TT);
+  explicit NVPTXMCAsmInfo(const Triple &TheTriple);
 };
 } // namespace llvm
 

Modified: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -37,7 +37,7 @@ static MCInstrInfo *createNVPTXMCInstrIn
   return X;
 }
 
-static MCRegisterInfo *createNVPTXMCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createNVPTXMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   // PTX does not have a return address register.
   InitNVPTXMCRegisterInfo(X, 0);
@@ -45,11 +45,11 @@ static MCRegisterInfo *createNVPTXMCRegi
 }
 
 static MCSubtargetInfo *
-createNVPTXMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) {
+createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   return createNVPTXMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const TargetTuple &TT,
+static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const Triple &TT,
                                                Reloc::Model RM,
                                                CodeModel::Model CM,
                                                CodeGenOpt::Level OL) {
@@ -61,7 +61,7 @@ static MCCodeGenInfo *createNVPTXMCCodeG
   return X;
 }
 
-static MCInstPrinter *createNVPTXMCInstPrinter(const TargetTuple &T,
+static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T,
                                                unsigned SyntaxVariant,
                                                const MCAsmInfo &MAI,
                                                const MCInstrInfo &MII,

Modified: llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp Tue Sep 15 11:17:27 2015
@@ -46,9 +46,8 @@ NVPTXSubtarget &NVPTXSubtarget::initiali
 NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS,
                                const NVPTXTargetMachine &TM)
-    : NVPTXGenSubtargetInfo(TargetTuple(TT), CPU, FS), PTXVersion(0),
-      SmVersion(20), TM(TM), InstrInfo(),
-      TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), TSInfo(),
+    : NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM),
+      InstrInfo(), TLInfo(TM, initializeSubtargetDependencies(CPU, FS)),
       FrameLowering() {}
 
 bool NVPTXSubtarget::hasImageHandles() const {

Modified: llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Tue Sep 15 11:17:27 2015
@@ -295,10 +295,10 @@ public:
                const MCTargetOptions &Options)
       : MCTargetAsmParser(Options), STI(STI), MII(MII) {
     // Check for 64-bit vs. 32-bit pointer mode.
-    const TargetTuple &TT = STI.getTargetTuple();
-    IsPPC64 = (TT.getArch() == TargetTuple::ppc64 ||
-               TT.getArch() == TargetTuple::ppc64le);
-    IsDarwin = TT.isMacOSX();
+    Triple TheTriple(STI.getTargetTriple());
+    IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
+               TheTriple.getArch() == Triple::ppc64le);
+    IsDarwin = TheTriple.isMacOSX();
     // Initialize the set of available features.
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
   }

Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Tue Sep 15 11:17:27 2015
@@ -230,11 +230,11 @@ namespace {
 
 MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const TargetTuple &TT, StringRef CPU) {
+                                        const Triple &TT, StringRef CPU) {
   if (TT.isOSDarwin())
     return new DarwinPPCAsmBackend(T);
 
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
-  bool IsLittleEndian = TT.getArch() == TargetTuple::ppc64le;
+  bool IsLittleEndian = TT.getArch() == Triple::ppc64le;
   return new ELFPPCAsmBackend(T, IsLittleEndian, OSABI);
 }

Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -12,13 +12,13 @@
 //===----------------------------------------------------------------------===//
 
 #include "PPCMCAsmInfo.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 
 using namespace llvm;
 
 void PPCMCAsmInfoDarwin::anchor() { }
 
-PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const TargetTuple &TT) {
+PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const Triple& T) {
   if (is64Bit) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
@@ -36,7 +36,7 @@ PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(b
   // The installed assembler for OSX < 10.6 lacks some directives.
   // FIXME: this should really be a check on the assembler characteristics
   // rather than OS version
-  if (TT.isMacOSX() && TT.isMacOSXVersionLT(10, 6))
+  if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
     HasWeakDefCanBeHiddenDirective = false;
 
   UseIntegratedAssembler = true;
@@ -44,7 +44,7 @@ PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(b
 
 void PPCELFMCAsmInfo::anchor() { }
 
-PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const TargetTuple &TT) {
+PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const Triple& T) {
   // FIXME: This is not always needed. For example, it is not needed in the
   // v2 abi.
   NeedsLocalForSize = true;
@@ -52,7 +52,7 @@ PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is
   if (is64Bit) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
-  IsLittleEndian = TT.getArch() == TargetTuple::ppc64le;
+  IsLittleEndian = T.getArch() == Triple::ppc64le;
 
   // ".comm align is in bytes but .align is pow-2."
   AlignmentIsInBytes = false;

Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -18,20 +18,20 @@
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class TargetTuple;
+class Triple;
 
 class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit PPCMCAsmInfoDarwin(bool is64Bit, const TargetTuple &);
+  explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple &);
 };
 
 class PPCELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit PPCELFMCAsmInfo(bool is64Bit, const TargetTuple &);
+  explicit PPCELFMCAsmInfo(bool is64Bit, const Triple &);
 };
 
 } // namespace llvm

Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp Tue Sep 15 11:17:27 2015
@@ -309,9 +309,8 @@ unsigned PPCMCCodeEmitter::getTLSRegEnco
   // Return the thread-pointer register's encoding.
   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
-  const TargetTuple &TT = STI.getTargetTuple();
-  bool isPPC64 = TT.getArch() == TargetTuple::ppc64 ||
-                 TT.getArch() == TargetTuple::ppc64le;
+  const Triple &TT = STI.getTargetTriple();
+  bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
   return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
 }
 

Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -51,9 +51,9 @@ static MCInstrInfo *createPPCMCInstrInfo
   return X;
 }
 
-static MCRegisterInfo *createPPCMCRegisterInfo(const TargetTuple &TT) {
-  bool isPPC64 = (TT.getArch() == TargetTuple::ppc64 ||
-                  TT.getArch() == TargetTuple::ppc64le);
+static MCRegisterInfo *createPPCMCRegisterInfo(const Triple &TT) {
+  bool isPPC64 =
+      (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
   unsigned Flavour = isPPC64 ? 0 : 1;
   unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
 
@@ -62,21 +62,21 @@ static MCRegisterInfo *createPPCMCRegist
   return X;
 }
 
-static MCSubtargetInfo *createPPCMCSubtargetInfo(const TargetTuple &TT,
+static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
                                                  StringRef CPU, StringRef FS) {
   return createPPCMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
-                                     const TargetTuple &TT) {
-  bool isPPC64 = (TT.getArch() == TargetTuple::ppc64 ||
-                  TT.getArch() == TargetTuple::ppc64le);
+                                     const Triple &TheTriple) {
+  bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
+                  TheTriple.getArch() == Triple::ppc64le);
 
   MCAsmInfo *MAI;
-  if (TT.isOSDarwin())
-    MAI = new PPCMCAsmInfoDarwin(isPPC64, TT);
+  if (TheTriple.isOSDarwin())
+    MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
   else
-    MAI = new PPCELFMCAsmInfo(isPPC64, TT);
+    MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple);
 
   // Initial state of the frame pointer is R1.
   unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
@@ -87,8 +87,7 @@ static MCAsmInfo *createPPCMCAsmInfo(con
   return MAI;
 }
 
-static MCCodeGenInfo *createPPCMCCodeGenInfo(const TargetTuple &TT,
-                                             Reloc::Model RM,
+static MCCodeGenInfo *createPPCMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
@@ -100,8 +99,8 @@ static MCCodeGenInfo *createPPCMCCodeGen
       RM = Reloc::Static;
   }
   if (CM == CodeModel::Default) {
-    if (!TT.isOSDarwin() && (TT.getArch() == TargetTuple::ppc64 ||
-                             TT.getArch() == TargetTuple::ppc64le))
+    if (!TT.isOSDarwin() &&
+        (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
       CM = CodeModel::Medium;
   }
   X->initMCCodeGenInfo(RM, CM, OL);
@@ -226,18 +225,18 @@ static MCTargetStreamer *createAsmTarget
 
 static MCTargetStreamer *
 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
-  const TargetTuple &TT = STI.getTargetTuple();
+  const Triple &TT = STI.getTargetTriple();
   if (TT.isOSBinFormatELF())
     return new PPCTargetELFStreamer(S);
   return new PPCTargetMachOStreamer(S);
 }
 
-static MCInstPrinter *createPPCMCInstPrinter(const TargetTuple &TT,
+static MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
                                              unsigned SyntaxVariant,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,
                                              const MCRegisterInfo &MRI) {
-  return new PPCInstPrinter(MAI, MII, MRI, TT.isOSDarwin());
+  return new PPCInstPrinter(MAI, MII, MRI, T.isOSDarwin());
 }
 
 extern "C" void LLVMInitializePowerPCTargetMC() {

Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h Tue Sep 15 11:17:27 2015
@@ -29,7 +29,7 @@ class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class Target;
-class TargetTuple;
+class Triple;
 class StringRef;
 class raw_pwrite_stream;
 class raw_ostream;
@@ -43,7 +43,7 @@ MCCodeEmitter *createPPCMCCodeEmitter(co
                                       MCContext &Ctx);
 
 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  const TargetTuple &TT, StringRef CPU);
+                                  const Triple &TT, StringRef CPU);
 
 /// Construct an PPC ELF object writer.
 MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,

Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Tue Sep 15 11:17:27 2015
@@ -49,7 +49,7 @@ PPCSubtarget &PPCSubtarget::initializeSu
 
 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const PPCTargetMachine &TM)
-    : PPCGenSubtargetInfo(TargetTuple(TT), CPU, FS), TargetTriple(TT),
+    : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
               TargetTriple.getArch() == Triple::ppc64le),
       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),

Modified: llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Tue Sep 15 11:17:27 2015
@@ -77,7 +77,7 @@ class SparcAsmParser : public MCTargetAs
   bool parseDirectiveWord(unsigned Size, SMLoc L);
 
   bool is64Bit() const {
-    return STI.getTargetTuple().getArch() == TargetTuple::sparcv9;
+    return STI.getTargetTriple().getArch() == Triple::sparcv9;
   }
 
   void expandSET(MCInst &Inst, SMLoc IDLoc,

Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp Tue Sep 15 11:17:27 2015
@@ -267,11 +267,10 @@ namespace {
   };
 
   class ELFSparcAsmBackend : public SparcAsmBackend {
-    TargetTuple::OSType OSType;
-
+    Triple::OSType OSType;
   public:
-    ELFSparcAsmBackend(const Target &T, TargetTuple::OSType OSType)
-        : SparcAsmBackend(T), OSType(OSType) {}
+    ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
+      SparcAsmBackend(T), OSType(OSType) { }
 
     void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                     uint64_t Value, bool IsPCRel) const override {
@@ -300,7 +299,6 @@ namespace {
 
 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          const TargetTuple &TT,
-                                          StringRef CPU) {
+                                          const Triple &TT, StringRef CPU) {
   return new ELFSparcAsmBackend(T, TT.getOS());
 }

Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -13,16 +13,16 @@
 
 #include "SparcMCAsmInfo.h"
 #include "SparcMCExpr.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCStreamer.h"
 
 using namespace llvm;
 
 void SparcELFMCAsmInfo::anchor() {}
 
-SparcELFMCAsmInfo::SparcELFMCAsmInfo(const TargetTuple &TT) {
-  bool isV9 = (TT.getArch() == TargetTuple::sparcv9);
-  IsLittleEndian = (TT.getArch() == TargetTuple::sparcel);
+SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Triple &TheTriple) {
+  bool isV9 = (TheTriple.getArch() == Triple::sparcv9);
+  IsLittleEndian = (TheTriple.getArch() == Triple::sparcel);
 
   if (isV9) {
     PointerSize = CalleeSaveStackSlotSize = 8;

Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -17,13 +17,13 @@
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class TargetTuple;
+class Triple;
 
 class SparcELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit SparcELFMCAsmInfo(const TargetTuple &TT);
+  explicit SparcELFMCAsmInfo(const Triple &TheTriple);
   const MCExpr*
   getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
                               MCStreamer &Streamer) const override;

Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -34,7 +34,7 @@ using namespace llvm;
 #include "SparcGenRegisterInfo.inc"
 
 static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI,
-                                       const TargetTuple &TT) {
+                                       const Triple &TT) {
   MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
   unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
@@ -43,7 +43,7 @@ static MCAsmInfo *createSparcMCAsmInfo(c
 }
 
 static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI,
-                                         const TargetTuple &TT) {
+                                         const Triple &TT) {
   MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
   unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
@@ -57,16 +57,16 @@ static MCInstrInfo *createSparcMCInstrIn
   return X;
 }
 
-static MCRegisterInfo *createSparcMCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitSparcMCRegisterInfo(X, SP::O7);
   return X;
 }
 
 static MCSubtargetInfo *
-createSparcMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) {
+createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   if (CPU.empty())
-    CPU = (TT.getArch() == TargetTuple::sparcv9) ? "v9" : "v8";
+    CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8";
   return createSparcMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
@@ -81,7 +81,7 @@ createSparcMCSubtargetInfo(const TargetT
 //
 // All code models require that the text segment is smaller than 2GB.
 
-static MCCodeGenInfo *createSparcMCCodeGenInfo(const TargetTuple &TT,
+static MCCodeGenInfo *createSparcMCCodeGenInfo(const Triple &TT,
                                                Reloc::Model RM,
                                                CodeModel::Model CM,
                                                CodeGenOpt::Level OL) {
@@ -99,7 +99,7 @@ static MCCodeGenInfo *createSparcMCCodeG
   return X;
 }
 
-static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const TargetTuple &TT,
+static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const Triple &TT,
                                                  Reloc::Model RM,
                                                  CodeModel::Model CM,
                                                  CodeGenOpt::Level OL) {
@@ -133,7 +133,7 @@ static MCTargetStreamer *createTargetAsm
   return new SparcTargetAsmStreamer(S, OS);
 }
 
-static MCInstPrinter *createSparcMCInstPrinter(const TargetTuple &TT,
+static MCInstPrinter *createSparcMCInstPrinter(const Triple &T,
                                                unsigned SyntaxVariant,
                                                const MCAsmInfo &MAI,
                                                const MCInstrInfo &MII,

Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h Tue Sep 15 11:17:27 2015
@@ -25,7 +25,7 @@ class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class Target;
-class TargetTuple;
+class Triple;
 class StringRef;
 class raw_pwrite_stream;
 class raw_ostream;
@@ -38,7 +38,7 @@ MCCodeEmitter *createSparcMCCodeEmitter(
                                         const MCRegisterInfo &MRI,
                                         MCContext &Ctx);
 MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const TargetTuple &TT, StringRef CPU);
+                                    const Triple &TT, StringRef CPU);
 MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
                                            bool IsLIttleEndian, uint8_t OSABI);
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Tue Sep 15 11:17:27 2015
@@ -52,7 +52,7 @@ SparcSubtarget &SparcSubtarget::initiali
 SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS, TargetMachine &TM,
                                bool is64Bit)
-    : SparcGenSubtargetInfo(TargetTuple(TT), CPU, FS), Is64Bit(is64Bit),
+    : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       FrameLowering(*this) {}
 

Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp Tue Sep 15 11:17:27 2015
@@ -111,8 +111,7 @@ bool SystemZMCAsmBackend::writeNopData(u
 
 MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
                                               const MCRegisterInfo &MRI,
-                                              const TargetTuple &TT,
-                                              StringRef CPU) {
+                                              const Triple &TT, StringRef CPU) {
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
   return new SystemZMCAsmBackend(OSABI);
 }

Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -13,7 +13,7 @@
 
 using namespace llvm;
 
-SystemZMCAsmInfo::SystemZMCAsmInfo(const TargetTuple &TT) {
+SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) {
   PointerSize = 8;
   CalleeSaveStackSlotSize = 8;
   IsLittleEndian = false;

Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -14,11 +14,11 @@
 #include "llvm/Support/Compiler.h"
 
 namespace llvm {
-class TargetTuple;
+class Triple;
 
 class SystemZMCAsmInfo : public MCAsmInfoELF {
 public:
-  explicit SystemZMCAsmInfo(const TargetTuple &TT);
+  explicit SystemZMCAsmInfo(const Triple &TT);
 };
 
 } // end namespace llvm

Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -132,7 +132,7 @@ unsigned SystemZMC::getFirstReg(unsigned
 }
 
 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
-                                         const TargetTuple &TT) {
+                                         const Triple &TT) {
   MCAsmInfo *MAI = new SystemZMCAsmInfo(TT);
   MCCFIInstruction Inst =
       MCCFIInstruction::createDefCfa(nullptr,
@@ -148,19 +148,18 @@ static MCInstrInfo *createSystemZMCInstr
   return X;
 }
 
-static MCRegisterInfo *createSystemZMCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitSystemZMCRegisterInfo(X, SystemZ::R14D);
   return X;
 }
 
-static MCSubtargetInfo *createSystemZMCSubtargetInfo(const TargetTuple &TT,
-                                                     StringRef CPU,
-                                                     StringRef FS) {
+static MCSubtargetInfo *
+createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   return createSystemZMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
-static MCCodeGenInfo *createSystemZMCCodeGenInfo(const TargetTuple &TT,
+static MCCodeGenInfo *createSystemZMCCodeGenInfo(const Triple &TT,
                                                  Reloc::Model RM,
                                                  CodeModel::Model CM,
                                                  CodeGenOpt::Level OL) {
@@ -208,7 +207,7 @@ static MCCodeGenInfo *createSystemZMCCod
   return X;
 }
 
-static MCInstPrinter *createSystemZMCInstPrinter(const TargetTuple &T,
+static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
                                                  unsigned SyntaxVariant,
                                                  const MCAsmInfo &MAI,
                                                  const MCInstrInfo &MII,

Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h Tue Sep 15 11:17:27 2015
@@ -23,7 +23,7 @@ class MCRegisterInfo;
 class MCSubtargetInfo;
 class StringRef;
 class Target;
-class TargetTuple;
+class Triple;
 class raw_pwrite_stream;
 class raw_ostream;
 
@@ -85,7 +85,7 @@ MCCodeEmitter *createSystemZMCCodeEmitte
 
 MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const TargetTuple &TT, StringRef CPU);
+                                        const Triple &TT, StringRef CPU);
 
 MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI);
 } // end namespace llvm

Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Tue Sep 15 11:17:27 2015
@@ -35,7 +35,7 @@ SystemZSubtarget::initializeSubtargetDep
 SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
                                    const TargetMachine &TM)
-    : SystemZGenSubtargetInfo(TargetTuple(TT), CPU, FS), HasDistinctOps(false),
+    : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
       HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
       HasPopulationCount(false), HasFastSerialization(false),
       HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),

Modified: llvm/trunk/lib/Target/TargetSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSubtargetInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetSubtargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetSubtargetInfo.cpp Tue Sep 15 11:17:27 2015
@@ -20,7 +20,7 @@ using namespace llvm;
 // TargetSubtargetInfo Class
 //
 TargetSubtargetInfo::TargetSubtargetInfo(
-    const TargetTuple &TT, StringRef CPU, StringRef FS,
+    const Triple &TT, StringRef CPU, StringRef FS,
     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
     const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
     const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp Tue Sep 15 11:17:27 2015
@@ -1068,8 +1068,8 @@ unsigned X86AsmInstrumentation::GetFrame
 X86AsmInstrumentation *
 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
                             const MCContext &Ctx, const MCSubtargetInfo &STI) {
-  const TargetTuple &TT = STI.getTargetTuple();
-  const bool hasCompilerRTSupport = TT.isOSLinux();
+  Triple T(STI.getTargetTriple());
+  const bool hasCompilerRTSupport = T.isOSLinux();
   if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
       MCOptions.SanitizeAddress) {
     if (STI.getFeatureBits()[X86::Mode32Bit] != 0)

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Tue Sep 15 11:17:27 2015
@@ -771,36 +771,36 @@ public:
 
 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
-                                           const TargetTuple &TT,
+                                           const Triple &TheTriple,
                                            StringRef CPU) {
-  if (TT.isOSBinFormatMachO())
+  if (TheTriple.isOSBinFormatMachO())
     return new DarwinX86_32AsmBackend(T, MRI, CPU);
 
-  if (TT.isOSWindows() && !TT.isOSBinFormatELF())
+  if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
     return new WindowsX86AsmBackend(T, false, CPU);
 
-  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
+  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
   return new ELFX86_32AsmBackend(T, OSABI, CPU);
 }
 
 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
-                                           const TargetTuple &TT,
+                                           const Triple &TheTriple,
                                            StringRef CPU) {
-  if (TT.isOSBinFormatMachO()) {
+  if (TheTriple.isOSBinFormatMachO()) {
     MachO::CPUSubTypeX86 CS =
-        StringSwitch<MachO::CPUSubTypeX86>(TT.getArchName())
+        StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
             .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
             .Default(MachO::CPU_SUBTYPE_X86_64_ALL);
     return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
   }
 
-  if (TT.isOSWindows() && !TT.isOSBinFormatELF())
+  if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
     return new WindowsX86AsmBackend(T, true, CPU);
 
-  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
+  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
 
-  if (TT.getEnvironment() == TargetTuple::GNUX32)
+  if (TheTriple.getEnvironment() == Triple::GNUX32)
     return new ELFX86_X32AsmBackend(T, OSABI, CPU);
   return new ELFX86_64AsmBackend(T, OSABI, CPU);
 }

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "X86MCAsmInfo.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCSectionELF.h"
@@ -41,8 +41,8 @@ MarkedJTDataRegions("mark-data-regions",
 
 void X86MCAsmInfoDarwin::anchor() { }
 
-X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const TargetTuple &TT) {
-  bool is64Bit = TT.getArch() == TargetTuple::x86_64;
+X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) {
+  bool is64Bit = T.getArch() == Triple::x86_64;
   if (is64Bit)
     PointerSize = CalleeSaveStackSlotSize = 8;
 
@@ -69,7 +69,7 @@ X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(c
   // old assembler lacks some directives
   // FIXME: this should really be a check on the assembler characteristics
   // rather than OS version
-  if (TT.isMacOSX() && TT.isMacOSXVersionLT(10, 6))
+  if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
     HasWeakDefCanBeHiddenDirective = false;
 
   // Assume ld64 is new enough that the abs-ified FDE relocs may be used
@@ -80,14 +80,15 @@ X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(c
   UseIntegratedAssembler = true;
 }
 
-X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const TargetTuple &TT)
-    : X86MCAsmInfoDarwin(TT) {}
+X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple)
+  : X86MCAsmInfoDarwin(Triple) {
+}
 
 void X86ELFMCAsmInfo::anchor() { }
 
-X86ELFMCAsmInfo::X86ELFMCAsmInfo(const TargetTuple &TT) {
-  bool is64Bit = TT.getArch() == TargetTuple::x86_64;
-  bool isX32 = TT.getEnvironment() == TargetTuple::GNUX32;
+X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) {
+  bool is64Bit = T.getArch() == Triple::x86_64;
+  bool isX32 = T.getEnvironment() == Triple::GNUX32;
 
   // For ELF, x86-64 pointer size depends on the ABI.
   // For x86-64 without the x32 ABI, pointer size is 8. For x86 and for x86-64
@@ -125,8 +126,8 @@ X86_64MCAsmInfoDarwin::getExprForPersona
 
 void X86MCAsmInfoMicrosoft::anchor() { }
 
-X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const TargetTuple &TT) {
-  if (TT.getArch() == TargetTuple::x86_64) {
+X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) {
+  if (Triple.getArch() == Triple::x86_64) {
     PrivateGlobalPrefix = ".L";
     PrivateLabelPrefix = ".L";
     PointerSize = 8;
@@ -151,9 +152,9 @@ X86MCAsmInfoMicrosoft::X86MCAsmInfoMicro
 
 void X86MCAsmInfoGNUCOFF::anchor() { }
 
-X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const TargetTuple &TT) {
-  assert(TT.isOSWindows() && "Windows is the only supported COFF target");
-  if (TT.getArch() == TargetTuple::x86_64) {
+X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) {
+  assert(Triple.isOSWindows() && "Windows is the only supported COFF target");
+  if (Triple.getArch() == Triple::x86_64) {
     PrivateGlobalPrefix = ".L";
     PrivateLabelPrefix = ".L";
     PointerSize = 8;

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -20,17 +20,17 @@
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class TargetTuple;
+class Triple;
 
 class X86MCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit X86MCAsmInfoDarwin(const TargetTuple &TT);
+  explicit X86MCAsmInfoDarwin(const Triple &Triple);
 };
 
 struct X86_64MCAsmInfoDarwin : public X86MCAsmInfoDarwin {
-  explicit X86_64MCAsmInfoDarwin(const TargetTuple &TT);
+  explicit X86_64MCAsmInfoDarwin(const Triple &Triple);
   const MCExpr *
   getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
                               MCStreamer &Streamer) const override;
@@ -40,21 +40,21 @@ class X86ELFMCAsmInfo : public MCAsmInfo
   void anchor() override;
 
 public:
-  explicit X86ELFMCAsmInfo(const TargetTuple &TT);
+  explicit X86ELFMCAsmInfo(const Triple &Triple);
 };
 
 class X86MCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
   void anchor() override;
 
 public:
-  explicit X86MCAsmInfoMicrosoft(const TargetTuple &TT);
+  explicit X86MCAsmInfoMicrosoft(const Triple &Triple);
 };
 
 class X86MCAsmInfoGNUCOFF : public MCAsmInfoGNUCOFF {
   void anchor() override;
 
 public:
-  explicit X86MCAsmInfoGNUCOFF(const TargetTuple &TT);
+  explicit X86MCAsmInfoGNUCOFF(const Triple &Triple);
 };
 } // namespace llvm
 

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -15,7 +15,7 @@
 #include "InstPrinter/X86ATTInstPrinter.h"
 #include "InstPrinter/X86IntelInstPrinter.h"
 #include "X86MCAsmInfo.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
@@ -42,11 +42,11 @@ using namespace llvm;
 #define GET_SUBTARGETINFO_MC_DESC
 #include "X86GenSubtargetInfo.inc"
 
-std::string X86_MC::ParseX86TargetTuple(const TargetTuple &TT) {
+std::string X86_MC::ParseX86Triple(const Triple &TT) {
   std::string FS;
-  if (TT.getArch() == TargetTuple::x86_64)
+  if (TT.getArch() == Triple::x86_64)
     FS = "+64bit-mode,-32bit-mode,-16bit-mode";
-  else if (TT.getEnvironment() != TargetTuple::CODE16)
+  else if (TT.getEnvironment() != Triple::CODE16)
     FS = "-64bit-mode,+32bit-mode,-16bit-mode";
   else
     FS = "-64bit-mode,-32bit-mode,+16bit-mode";
@@ -54,8 +54,8 @@ std::string X86_MC::ParseX86TargetTuple(
   return FS;
 }
 
-unsigned X86_MC::getDwarfRegFlavour(const TargetTuple &TT, bool isEH) {
-  if (TT.getArch() == TargetTuple::x86_64)
+unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
+  if (TT.getArch() == Triple::x86_64)
     return DWARFFlavour::X86_64;
 
   if (TT.isOSDarwin())
@@ -74,9 +74,9 @@ void X86_MC::InitLLVM2SEHRegisterMapping
   }
 }
 
-MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const TargetTuple &TT,
+MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
                                                   StringRef CPU, StringRef FS) {
-  std::string ArchFS = X86_MC::ParseX86TargetTuple(TT);
+  std::string ArchFS = X86_MC::ParseX86Triple(TT);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
@@ -97,8 +97,8 @@ static MCInstrInfo *createX86MCInstrInfo
   return X;
 }
 
-static MCRegisterInfo *createX86MCRegisterInfo(const TargetTuple &TT) {
-  unsigned RA = (TT.getArch() == TargetTuple::x86_64)
+static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
+  unsigned RA = (TT.getArch() == Triple::x86_64)
                     ? X86::RIP  // Should have dwarf #16.
                     : X86::EIP; // Should have dwarf #8.
 
@@ -110,26 +110,27 @@ static MCRegisterInfo *createX86MCRegist
 }
 
 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
-                                     const TargetTuple &TT) {
-  bool is64Bit = TT.getArch() == TargetTuple::x86_64;
+                                     const Triple &TheTriple) {
+  bool is64Bit = TheTriple.getArch() == Triple::x86_64;
 
   MCAsmInfo *MAI;
-  if (TT.isOSBinFormatMachO()) {
+  if (TheTriple.isOSBinFormatMachO()) {
     if (is64Bit)
-      MAI = new X86_64MCAsmInfoDarwin(TT);
+      MAI = new X86_64MCAsmInfoDarwin(TheTriple);
     else
-      MAI = new X86MCAsmInfoDarwin(TT);
-  } else if (TT.isOSBinFormatELF()) {
+      MAI = new X86MCAsmInfoDarwin(TheTriple);
+  } else if (TheTriple.isOSBinFormatELF()) {
     // Force the use of an ELF container.
-    MAI = new X86ELFMCAsmInfo(TT);
-  } else if (TT.isWindowsMSVCEnvironment() ||
-             TT.isWindowsCoreCLREnvironment()) {
-    MAI = new X86MCAsmInfoMicrosoft(TT);
-  } else if (TT.isOSCygMing() || TT.isWindowsItaniumEnvironment()) {
-    MAI = new X86MCAsmInfoGNUCOFF(TT);
+    MAI = new X86ELFMCAsmInfo(TheTriple);
+  } else if (TheTriple.isWindowsMSVCEnvironment() ||
+             TheTriple.isWindowsCoreCLREnvironment()) {
+    MAI = new X86MCAsmInfoMicrosoft(TheTriple);
+  } else if (TheTriple.isOSCygMing() ||
+             TheTriple.isWindowsItaniumEnvironment()) {
+    MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
   } else {
     // The default is ELF.
-    MAI = new X86ELFMCAsmInfo(TT);
+    MAI = new X86ELFMCAsmInfo(TheTriple);
   }
 
   // Initialize initial frame state.
@@ -151,13 +152,12 @@ static MCAsmInfo *createX86MCAsmInfo(con
   return MAI;
 }
 
-static MCCodeGenInfo *createX86MCCodeGenInfo(const TargetTuple &TT,
-                                             Reloc::Model RM,
+static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
-  bool is64Bit = TT.getArch() == TargetTuple::x86_64;
+  bool is64Bit = TT.getArch() == Triple::x86_64;
 
   if (RM == Reloc::Default) {
     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
@@ -201,7 +201,7 @@ static MCCodeGenInfo *createX86MCCodeGen
   return X;
 }
 
-static MCInstPrinter *createX86MCInstPrinter(const TargetTuple &TT,
+static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
                                              unsigned SyntaxVariant,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,
@@ -213,14 +213,14 @@ static MCInstPrinter *createX86MCInstPri
   return nullptr;
 }
 
-static MCRelocationInfo *createX86MCRelocationInfo(const TargetTuple &TT,
+static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
                                                    MCContext &Ctx) {
-  if (TT.isOSBinFormatMachO() && TT.getArch() == TargetTuple::x86_64)
+  if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64)
     return createX86_64MachORelocationInfo(Ctx);
-  else if (TT.isOSBinFormatELF())
+  else if (TheTriple.isOSBinFormatELF())
     return createX86_64ELFRelocationInfo(Ctx);
   // Default to the stock relocation info.
-  return llvm::createMCRelocationInfo(TT, Ctx);
+  return llvm::createMCRelocationInfo(TheTriple, Ctx);
 }
 
 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Tue Sep 15 11:17:27 2015
@@ -28,7 +28,7 @@ class MCSubtargetInfo;
 class MCRelocationInfo;
 class MCStreamer;
 class Target;
-class TargetTuple;
+class Triple;
 class StringRef;
 class raw_ostream;
 class raw_pwrite_stream;
@@ -52,15 +52,15 @@ namespace N86 {
 }
 
 namespace X86_MC {
-std::string ParseX86TargetTuple(const TargetTuple &TT);
+std::string ParseX86Triple(const Triple &TT);
 
-unsigned getDwarfRegFlavour(const TargetTuple &TT, bool isEH);
+unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
 
 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
 
 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
-MCSubtargetInfo *createX86MCSubtargetInfo(const TargetTuple &TT, StringRef CPU,
+MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
@@ -69,9 +69,9 @@ MCCodeEmitter *createX86MCCodeEmitter(co
                                       MCContext &Ctx);
 
 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                     const TargetTuple &TT, StringRef CPU);
+                                     const Triple &TT, StringRef CPU);
 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                     const TargetTuple &TT, StringRef CPU);
+                                     const Triple &TT, StringRef CPU);
 
 /// Construct an X86 Windows COFF machine code streamer which will generate
 /// PE/COFF format object files.

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Sep 15 11:17:27 2015
@@ -50,8 +50,8 @@ EnableBasePointer("x86-use-base-pointer"
 
 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
     : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
-                         X86_MC::getDwarfRegFlavour(TargetTuple(TT), false),
-                         X86_MC::getDwarfRegFlavour(TargetTuple(TT), true),
+                         X86_MC::getDwarfRegFlavour(TT, false),
+                         X86_MC::getDwarfRegFlavour(TT, true),
                          (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
   X86_MC::InitLLVM2SEHRegisterMapping(this);
 

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Tue Sep 15 11:17:27 2015
@@ -290,7 +290,7 @@ X86Subtarget &X86Subtarget::initializeSu
 X86Subtarget::X86Subtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS, const X86TargetMachine &TM,
                            unsigned StackAlignOverride)
-    : X86GenSubtargetInfo(TargetTuple(TT), CPU, FS), X86ProcFamily(Others),
+    : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
       PICStyle(PICStyles::None), TargetTriple(TT),
       StackAlignOverride(StackAlignOverride),
       In64BitMode(TargetTriple.getArch() == Triple::x86_64),

Modified: llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp Tue Sep 15 11:17:27 2015
@@ -12,7 +12,7 @@ using namespace llvm;
 
 void XCoreMCAsmInfo::anchor() { }
 
-XCoreMCAsmInfo::XCoreMCAsmInfo(const TargetTuple &TT) {
+XCoreMCAsmInfo::XCoreMCAsmInfo(const Triple &TT) {
   SupportsDebugInformation = true;
   Data16bitsDirective = "\t.short\t";
   Data32bitsDirective = "\t.long\t";

Modified: llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h Tue Sep 15 11:17:27 2015
@@ -17,13 +17,13 @@
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class TargetTuple;
+class Triple;
 
 class XCoreMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit XCoreMCAsmInfo(const TargetTuple &TT);
+  explicit XCoreMCAsmInfo(const Triple &TT);
 };
 
 } // namespace llvm

Modified: llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp Tue Sep 15 11:17:27 2015
@@ -40,19 +40,19 @@ static MCInstrInfo *createXCoreMCInstrIn
   return X;
 }
 
-static MCRegisterInfo *createXCoreMCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createXCoreMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitXCoreMCRegisterInfo(X, XCore::LR);
   return X;
 }
 
 static MCSubtargetInfo *
-createXCoreMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) {
+createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   return createXCoreMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
-                                       const TargetTuple &TT) {
+                                       const Triple &TT) {
   MCAsmInfo *MAI = new XCoreMCAsmInfo(TT);
 
   // Initial state of the frame pointer is SP.
@@ -62,7 +62,7 @@ static MCAsmInfo *createXCoreMCAsmInfo(c
   return MAI;
 }
 
-static MCCodeGenInfo *createXCoreMCCodeGenInfo(const TargetTuple &TT,
+static MCCodeGenInfo *createXCoreMCCodeGenInfo(const Triple &TT,
                                                Reloc::Model RM,
                                                CodeModel::Model CM,
                                                CodeGenOpt::Level OL) {
@@ -80,7 +80,7 @@ static MCCodeGenInfo *createXCoreMCCodeG
   return X;
 }
 
-static MCInstPrinter *createXCoreMCInstPrinter(const TargetTuple &T,
+static MCInstPrinter *createXCoreMCInstPrinter(const Triple &T,
                                                unsigned SyntaxVariant,
                                                const MCAsmInfo &MAI,
                                                const MCInstrInfo &MII,

Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Tue Sep 15 11:17:27 2015
@@ -27,5 +27,5 @@ void XCoreSubtarget::anchor() { }
 
 XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS, const TargetMachine &TM)
-    : XCoreGenSubtargetInfo(TargetTuple(TT), CPU, FS), InstrInfo(),
-      FrameLowering(*this), TLInfo(TM, *this), TSInfo() {}
+    : XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
+      TLInfo(TM, *this), TSInfo() {}

Modified: llvm/trunk/tools/dsymutil/DwarfLinker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/dsymutil/DwarfLinker.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/tools/dsymutil/DwarfLinker.cpp (original)
+++ llvm/trunk/tools/dsymutil/DwarfLinker.cpp Tue Sep 15 11:17:27 2015
@@ -595,8 +595,8 @@ bool DwarfStreamer::init(Triple TheTripl
   if (EC)
     return error(Twine(OutputFilename) + ": " + EC.message(), Context);
 
-  MS = TheTarget->createMCObjectStreamer(TargetTuple(TheTriple), *MC, *MAB,
-                                         *OutFile, MCE, *MSTI, false,
+  MS = TheTarget->createMCObjectStreamer(TheTriple, *MC, *MAB, *OutFile, MCE,
+                                         *MSTI, false,
                                          /*DWARFMustBeAtTheEnd*/ false);
   if (!MS)
     return error("no object streamer for target " + TripleName, Context);

Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Tue Sep 15 11:17:27 2015
@@ -477,8 +477,8 @@ int main(int argc, char **argv) {
 
   MCInstPrinter *IP = nullptr;
   if (FileType == OFT_AssemblyFile) {
-    IP = TheTarget->createMCInstPrinter(TargetTuple(Triple(TripleName)),
-                                        OutputAsmVariant, *MAI, *MCII, *MRI);
+    IP = TheTarget->createMCInstPrinter(Triple(TripleName), OutputAsmVariant,
+                                        *MAI, *MCII, *MRI);
 
     // Set the display preference for hex vs. decimal immediates.
     IP->setPrintImmHex(PrintImmHex);
@@ -510,8 +510,8 @@ int main(int argc, char **argv) {
 
     MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
     MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
-    Str.reset(TheTarget->createMCObjectStreamer(TargetTuple(TheTriple), Ctx,
-                                                *MAB, *OS, CE, *STI, RelaxAll,
+    Str.reset(TheTarget->createMCObjectStreamer(TheTriple, Ctx, *MAB, *OS, CE,
+                                                *STI, RelaxAll,
                                                 /*DWARFMustBeAtTheEnd*/ false));
     if (NoExecStack)
       Str->InitSections(true);

Modified: llvm/trunk/tools/llvm-objdump/MachODump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/MachODump.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/MachODump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/MachODump.cpp Tue Sep 15 11:17:27 2015
@@ -5910,8 +5910,7 @@ static void DisassembleMachO(StringRef F
   }
   int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
   std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
-      TargetTuple(Triple(TripleName)), AsmPrinterVariant, *AsmInfo, *InstrInfo,
-      *MRI));
+      Triple(TripleName), AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI));
   // Set the display preference for hex vs. decimal immediates.
   IP->setPrintImmHex(PrintImmHex);
   // Comment stream and backing vector.
@@ -5959,8 +5958,8 @@ static void DisassembleMachO(StringRef F
     }
     int ThumbAsmPrinterVariant = ThumbAsmInfo->getAssemblerDialect();
     ThumbIP.reset(ThumbTarget->createMCInstPrinter(
-        TargetTuple(Triple(ThumbTripleName)), ThumbAsmPrinterVariant,
-        *ThumbAsmInfo, *ThumbInstrInfo, *ThumbMRI));
+        Triple(ThumbTripleName), ThumbAsmPrinterVariant, *ThumbAsmInfo,
+        *ThumbInstrInfo, *ThumbMRI));
     // Set the display preference for hex vs. decimal immediates.
     ThumbIP->setPrintImmHex(PrintImmHex);
   }

Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Tue Sep 15 11:17:27 2015
@@ -861,9 +861,8 @@ static void DisassembleObject(const Obje
       TheTarget->createMCInstrAnalysis(MII.get()));
 
   int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
-  std::unique_ptr<MCInstPrinter> IP(
-      TheTarget->createMCInstPrinter(TargetTuple(Triple(TripleName)),
-                                     AsmPrinterVariant, *AsmInfo, *MII, *MRI));
+  std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
+      Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MRI));
   if (!IP) {
     errs() << "error: no instruction printer for target " << TripleName
       << '\n';

Modified: llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp (original)
+++ llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp Tue Sep 15 11:17:27 2015
@@ -604,8 +604,8 @@ static int linkAndVerify() {
 
   std::unique_ptr<MCInstrInfo> MII(TheTarget->createMCInstrInfo());
 
-  std::unique_ptr<MCInstPrinter> InstPrinter(TheTarget->createMCInstPrinter(
-      TargetTuple(Triple(TripleName)), 0, *MAI, *MII, *MRI));
+  std::unique_ptr<MCInstPrinter> InstPrinter(
+      TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MRI));
 
   // Load any dylibs requested on the command line.
   loadDylibs();

Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=247702&r1=247701&r2=247702&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Tue Sep 15 11:17:27 2015
@@ -1437,7 +1437,7 @@ void SubtargetEmitter::run(raw_ostream &
   // MCInstrInfo initialization routine.
   OS << "static inline MCSubtargetInfo *create" << Target
      << "MCSubtargetInfoImpl("
-     << "const TargetTuple &TT, StringRef CPU, StringRef FS) {\n";
+     << "const Triple &TT, StringRef CPU, StringRef FS) {\n";
   OS << "  return new MCSubtargetInfo(TT, CPU, FS, ";
   if (NumFeatures)
     OS << Target << "FeatureKV, ";
@@ -1482,7 +1482,7 @@ void SubtargetEmitter::run(raw_ostream &
   OS << "namespace llvm {\n";
   OS << "class DFAPacketizer;\n";
   OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
-     << "  explicit " << ClassName << "(const TargetTuple &TT, StringRef CPU, "
+     << "  explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
      << "StringRef FS);\n"
      << "public:\n"
      << "  unsigned resolveSchedClass(unsigned SchedClass, "
@@ -1516,8 +1516,8 @@ void SubtargetEmitter::run(raw_ostream &
     OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
   }
 
-  OS << ClassName << "::" << ClassName
-     << "(const TargetTuple &TT, StringRef CPU, StringRef FS)\n"
+  OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
+     << "StringRef FS)\n"
      << "  : TargetSubtargetInfo(TT, CPU, FS, ";
   if (NumFeatures)
     OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";




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