[PATCH] D12635: merge vector stores into wider vector stores and fix AArch64 misaligned access TLI hook (PR21711)

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 11 14:35:22 PDT 2015

arsenm added inline comments.

Comment at: test/CodeGen/AArch64/merge-store.ll:30
@@ +29,3 @@
+define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) {
+  %idx0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3
spatel wrote:
> arsenm wrote:
> > Can you add some more test cases with different combination sized vectors? I would like to see a testcase that might try to combine multiple 3x vectors
> I've been trying to find a way to do this, but all attempts so far have been thwarted because things like a v3f32 are not a simple type, so MergeConsecutiveStores doesn't get very far. Do you have a specific pattern that you're thinking of? Keep in mind that this patch limits vector merging only to extracted elements of a vector, so we're not even handling loads yet.
I was thinking in case you had something like load v3i32, load v3i32 and those might d be legalized 
into v2i32, i32, v2i32, i32 so you would have mixed scalar and vector loads to worry about.

I forgot that MergeConsecutiveStores currently only runs before types are legal, so this won't really do anything for now, although I would eventually like to run it again later and to handle 3 vectors


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