[PATCH] D12753: AVX-512: Fixed a bug in FSUB lowering

[Elena Demikhovsky via llvm-commits]

delena created this revision.
delena added a reviewer: igorb.
delena added a subscriber: llvm-commits.
delena set the repository for this revision to rL LLVM.

The compiler failed to lower X86ISD::FXOR node for 512-bit data type on KNL because VXORPS-zmm is supported in DQ instruction set.
The solution is using integer XOR - VPXOR*.

(The X86ISD::FOR is the same but nobody generates X86ISD::FOR for 512-bit data types).


Repository:
  rL LLVM

http://reviews.llvm.org/D12753

Files:
  ../lib/Target/X86/X86ISelLowering.cpp
  ../test/CodeGen/X86/avx512-arith.ll

Index: ../test/CodeGen/X86/avx512-arith.ll
===================================================================
--- ../test/CodeGen/X86/avx512-arith.ll
+++ ../test/CodeGen/X86/avx512-arith.ll
@@ -652,3 +652,13 @@
   %r = select <8 x i1> %mask, <8 x double> %x, <8 x double> zeroinitializer
   ret <8 x double> %r
 }
+
+; CHECK-LABEL: test_fxor
+; CHECK: vpxord
+; CHECK: ret
+define <16 x float>  @test_fxor(<16 x float> %a) {
+
+  %res = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a
+  ret <16 x float>%res
+}
+
Index: ../lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- ../lib/Target/X86/X86ISelLowering.cpp
+++ ../lib/Target/X86/X86ISelLowering.cpp
@@ -25134,7 +25134,8 @@
 }
 
 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
-static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
+static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
+                                 const X86Subtarget *Subtarget) {
   assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
 
   // F[X]OR(0.0, x) -> x
@@ -25146,6 +25147,19 @@
   if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
     if (C->getValueAPF().isPosZero())
       return N->getOperand(0);
+
+  EVT VT = N->getValueType(0);
+  if (VT.is512BitVector() && !Subtarget->hasDQI()) {
+    SDLoc dl(N);
+    MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
+    MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
+
+    SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
+    SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
+    unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
+    SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
+    return  DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
+  }
   return SDValue();
 }
 
@@ -26009,7 +26023,7 @@
   case ISD::FADD:           return PerformFADDCombine(N, DAG, Subtarget);
   case ISD::FSUB:           return PerformFSUBCombine(N, DAG, Subtarget);
   case X86ISD::FXOR:
-  case X86ISD::FOR:         return PerformFORCombine(N, DAG);
+  case X86ISD::FOR:         return PerformFORCombine(N, DAG, Subtarget);
   case X86ISD::FMIN:
   case X86ISD::FMAX:        return PerformFMinFMaxCombine(N, DAG);
   case X86ISD::FAND:        return PerformFANDCombine(N, DAG);


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