[PATCH] D12730: [mips] Unified the MipsMemSimm9GPRAsmOperand and MipsMemSimm9AsmOperand functions, NFC.

[Scott Egerton via llvm-commits]

s.egerton created this revision.
s.egerton added reviewers: dsanders, vkalintiris.
s.egerton added a subscriber: llvm-commits.

These functions had the same purpose, however the MipsMemSimm9GPRAsmOperand
function was only for micromips32r6 and the MipsMemSimm9AsmOperand did not
have a ParserMatchClass.

http://reviews.llvm.org/D12730

Files:
  lib/Target/Mips/AsmParser/MipsAsmParser.cpp
  lib/Target/Mips/MicroMips32r6InstrInfo.td
  lib/Target/Mips/MipsInstrInfo.td

Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -449,6 +449,14 @@
   let ParserMethod = "parseMemOperand";
 }
 
+def MipsMemSimm9AsmOperand : AsmOperandClass {
+  let Name = "MemOffsetSimm9";
+  let SuperClasses = [MipsMemAsmOperand];
+  let RenderMethod = "addMemOperands";
+  let ParserMethod = "parseMemOperand";
+  let PredicateMethod = "isMemWithSimmOffset<9>";
+}
+
 def MipsMemSimm11AsmOperand : AsmOperandClass {
   let Name = "MemOffsetSimm11";
   let SuperClasses = [MipsMemAsmOperand];
@@ -499,6 +507,7 @@
 def mem_simm9 : mem_generic {
   let MIOperandInfo = (ops ptr_rc, simm9);
   let EncoderMethod = "getMemEncoding";
+  let ParserMatchClass = MipsMemSimm9AsmOperand;
 }
 
 def mem_simm11 : mem_generic {
Index: lib/Target/Mips/MicroMips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -170,26 +170,6 @@
 
 //===----------------------------------------------------------------------===//
 //
-// Operand Definitions
-//
-//===----------------------------------------------------------------------===//
-
-def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
-  let Name = "MemOffsetSimm9GPR";
-  let SuperClasses = [MipsMemAsmOperand];
-  let RenderMethod = "addMemOperands";
-  let ParserMethod = "parseMemOperand";
-  let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
-}
-
-def mem_simm9gpr : mem_generic {
-  let MIOperandInfo = (ops ptr_rc, simm9);
-  let EncoderMethod = "getMemEncoding";
-  let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
-}
-
-//===----------------------------------------------------------------------===//
-//
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
@@ -390,7 +370,7 @@
   let mayStore = 1;
 }
 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
-class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9gpr>;
+class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
 
 /// Floating Point Instructions
 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -957,9 +957,6 @@
     return isMem() && dyn_cast<MCConstantExpr>(getMemOff());
   }
   template <unsigned Bits> bool isMemWithSimmOffset() const {
-    return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff());
-  }
-  template <unsigned Bits> bool isMemWithSimmOffsetGPR() const {
     return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
       && getMemBase()->isGPRAsmReg();
   }


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