[llvm] r247008 - [WebAssembly] Enable SSA lowering and other pre-regalloc passes

[JF Bastien via llvm-commits]

On Tue, Sep 8, 2015 at 5:39 AM, Dan Gohman via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: djg
> Date: Tue Sep  8 07:39:25 2015
> New Revision: 247008
>
> URL: http://llvm.org/viewvc/llvm-project?rev=247008&view=rev
> Log:
> [WebAssembly] Enable SSA lowering and other pre-regalloc passes
>
> Added:
>     llvm/trunk/test/CodeGen/WebAssembly/phi.ll
> Modified:
>     llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
>
> Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp?rev=247008&r1=247007&r2=247008&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp Tue Sep  8 07:39:25 2015
> @@ -164,7 +164,27 @@ bool WebAssemblyPassConfig::addILPOpts()
>
>  void WebAssemblyPassConfig::addPreRegAlloc() {}
>
> -void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {}
> +void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {
> +  // This is list is derived from the regalloc pass list used in

Too many "is" :-)

> +  // addFastRegAlloc and addOptimizedRegAlloc in lib/CodeGen/Passes.cpp. We
> +  // don't run the actual register allocator, but we do run the passes which
> +  // lower SSA form, so after these passes are complete, we have non-SSA
> +  // virtual registers.
> +
> +  if (Optimized) {
> +    addPass(&ProcessImplicitDefsID);
> +    addPass(&LiveVariablesID);
> +    addPass(&MachineLoopInfoID);
> +  }
> +
> +  addPass(&PHIEliminationID);
> +  addPass(&TwoAddressInstructionPassID, false);
> +
> +  if (Optimized) {
> +    addPass(&RegisterCoalescerID);
> +    addPass(&MachineSchedulerID);
> +  }
> +}
>
>  void WebAssemblyPassConfig::addPostRegAlloc() {
>    // FIXME: the following passes dislike virtual registers. Disable them for now
>
> Added: llvm/trunk/test/CodeGen/WebAssembly/phi.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/phi.ll?rev=247008&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/WebAssembly/phi.ll (added)
> +++ llvm/trunk/test/CodeGen/WebAssembly/phi.ll Tue Sep  8 07:39:25 2015
> @@ -0,0 +1,22 @@
> +; RUN: llc < %s -asm-verbose=false | FileCheck %s
> +
> +; Test that phis are lowered.
> +
> +target datalayout = "e-p:32:32-i64:64-v128:8:128-n32:64-S128"
> +target triple = "wasm32-unknown-unknown"
> +
> +; CHECK-LABEL: test0
> +; CHECK: (setlocal [[REG:@.*]] (argument 0))
> +; CHECK: (setlocal [[REG]] (sdiv [[REG]] {{.*}}))
> +; CHECK: (return [[REG]])
> +define i32 @test0(i32 %p) {
> +entry:
> +  %t = icmp slt i32 %p, 0
> +  br i1 %t, label %true, label %done
> +true:
> +  %a = sdiv i32 %p, 3
> +  br label %done
> +done:
> +  %s = phi i32 [ %a, %true ], [ %p, %entry ]
> +  ret i32 %s
> +}
>
>
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