[llvm] r246805 - [PowerPC] Compute the MMO offset for an unaligned load with signed arithmetic

[Hal Finkel via llvm-commits]

Author: hfinkel
Date: Thu Sep  3 16:12:15 2015
New Revision: 246805

URL: http://llvm.org/viewvc/llvm-project?rev=246805&view=rev
Log:
[PowerPC] Compute the MMO offset for an unaligned load with signed arithmetic

If you compute the MMO offset using unsigned arithmetic, you end up with a
large positive offset instead of a small negative one. In theory, this could
cause bad instruction-scheduling decisions later.

I noticed this by inspection from the debug output, and using that for the
regression test is the best I can do right now.

Added:
    llvm/trunk/test/CodeGen/PowerPC/unal-vec-negarith.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=246805&r1=246804&r2=246805&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Sep  3 16:12:15 2015
@@ -10302,7 +10302,8 @@ SDValue PPCTargetLowering::PerformDAGCom
       // original unaligned load.
       MachineFunction &MF = DAG.getMachineFunction();
       MachineMemOperand *BaseMMO =
-        MF.getMachineMemOperand(LD->getMemOperand(), -MemVT.getStoreSize()+1,
+        MF.getMachineMemOperand(LD->getMemOperand(),
+                                -(long)MemVT.getStoreSize()+1,
                                 2*MemVT.getStoreSize()-1);
 
       // Create the new base load.

Added: llvm/trunk/test/CodeGen/PowerPC/unal-vec-negarith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/unal-vec-negarith.ll?rev=246805&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/unal-vec-negarith.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/unal-vec-negarith.ll Thu Sep  3 16:12:15 2015
@@ -0,0 +1,17 @@
+; RUN: llc -debug-only=isel <%s >%t 2>&1 && FileCheck <%t %s
+; REQUIRES: asserts
+
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define <16 x i8> @test_l_v16i8(<16 x i8>* %p) #0 {
+entry:
+  %r = load <16 x i8>, <16 x i8>* %p, align 1
+  ret <16 x i8> %r
+
+; CHECK-NOT: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<LD31[%p+4294967281](align=1)>
+; CHECK:     v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<LD31[%p+-15](align=1)>
+}
+
+attributes #0 = { nounwind "target-cpu"="pwr7" }
+