[PATCH] D12325: Improve ISel using across lane addition reduction

[James Molloy via llvm-commits]

jmolloy accepted this revision.
jmolloy added a comment.
This revision is now accepted and ready to land.

Hi,

This looks great now, thanks! LGTM with the few nitpicks below.

Cheers,

James


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8614
@@ +8613,3 @@
+
+  int NumExpectedStep = APInt(8, NumVecElts).logBase2();
+  SDValue PreOp = N0;
----------------
Pedantic: Step -> Steps.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8618
@@ +8617,3 @@
+  for (int CurStep = 0; CurStep != NumExpectedStep; ++CurStep) {
+    // We specifically check ADD for now.
+    if (PreOp.getOpcode() != ISD::ADD)
----------------
"check" -> "check only"

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8630
@@ +8629,3 @@
+    }
+    // Check if it forms a one step of the across vector reduction.
+    // E.g.,
----------------
"Check if it forms a one" -> "Check if it forms one"


http://reviews.llvm.org/D12325