[llvm] r246472 - [AArch64][CollectLOH] Remove an invalid assertion and add a test case exposing it.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Mon Aug 31 14:02:00 2015
New Revision: 246472

URL: http://llvm.org/viewvc/llvm-project?rev=246472&view=rev
Log:
[AArch64][CollectLOH] Remove an invalid assertion and add a test case exposing it.

rdar://problem/22491525

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp
    llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp?rev=246472&r1=246471&r2=246472&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp Mon Aug 31 14:02:00 2015
@@ -353,9 +353,17 @@ static void initReachingDef(const Machin
 
         for (MCRegAliasIterator AI(CurReg, TRI, true); AI.isValid(); ++AI) {
           MapRegToId::const_iterator ItRegId = RegToId.find(*AI);
-          assert(ItRegId != RegToId.end() &&
-                 "Sub-register of an "
-                 "involved register, not recorded as involved!");
+          // If this alias has not been recorded, then it is not interesting
+          // for the current analysis.
+          // We can end up in this situation because of tuple registers.
+          // E.g., Let say we are interested in S1. When we register
+          // S1, we will also register its aliases and in particular
+          // the tuple Q1_Q2.
+          // Now, when we encounter Q1_Q2, we will look through its aliases
+          // and will find that S2 is not registered.
+          if (ItRegId == RegToId.end())
+            continue;
+
           BBKillSet.set(ItRegId->second);
           BBGen[ItRegId->second] = &MI;
         }

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh.ll?rev=246472&r1=246471&r2=246472&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-collect-loh.ll Mon Aug 31 14:02:00 2015
@@ -622,3 +622,36 @@ define void @setL(<1 x i8> %t) {
   store <1 x i8> %t, <1 x i8>* @L, align 4
   ret void
 }
+
+; Make sure we do not assert when we do not track
+; all the aliases of a tuple register.
+; Indeed the tuple register can be tracked because of
+; one of its element, but the other elements of the tuple
+; do not need to be tracked and we used to assert on that.
+; Note: The test case is fragile in the sense that we need
+; a tuple register to appear in the lowering. Thus, the target
+; cpu is required to have the problem reproduced.
+; CHECK-LABEL: _uninterestingSub
+; CHECK: adrp [[ADRP_REG:x[0-9]+]], [[CONSTPOOL:lCPI[0-9]+_[0-9]+]]@PAGE
+; CHECK-NEXT: ldr q[[IDX:[0-9]+]], {{\[}}[[ADRP_REG]], [[CONSTPOOL]]@PAGEOFF]
+; The tuple comes from the next instruction.
+; CHECK-NEXT: tbl.16b v{{[0-9]+}}, { v{{[0-9]+}}, v{{[0-9]+}} }, v[[IDX]]
+; CHECK: ret
+define void @uninterestingSub(i8* nocapture %row) #0 {
+  %tmp = bitcast i8* %row to <16 x i8>*
+  %tmp1 = load <16 x i8>, <16 x i8>* %tmp, align 16
+  %vext43 = shufflevector <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> %tmp1, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
+  %add.i.414 = add <16 x i8> zeroinitializer, %vext43
+  store <16 x i8> %add.i.414, <16 x i8>* %tmp, align 16
+  %add.ptr51 = getelementptr inbounds i8, i8* %row, i64 16
+  %tmp2 = bitcast i8* %add.ptr51 to <16 x i8>*
+  %tmp3 = load <16 x i8>, <16 x i8>* %tmp2, align 16
+  %tmp4 = bitcast i8* undef to <16 x i8>*
+  %tmp5 = load <16 x i8>, <16 x i8>* %tmp4, align 16
+  %vext157 = shufflevector <16 x i8> %tmp3, <16 x i8> %tmp5, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
+  %add.i.402 = add <16 x i8> zeroinitializer, %vext157
+  store <16 x i8> %add.i.402, <16 x i8>* %tmp4, align 16
+  ret void
+}
+
+attributes #0 = { "target-cpu"="cyclone" }