[PATCH] D12479: [X86][AVX512BW] support in byte shift and SAD

[Elena Demikhovsky via llvm-commits]

delena added inline comments.

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Comment at: ../llvmTmp/lib/Target/X86/X86InstrAVX512.td:6788
@@ +6787,3 @@
+             !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+             [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i32 imm:$src2))))]>;
+  let mayLoad = 1 in
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While DAG lowering, we build SHIFT nodes with Imm8. I suppose that Imm32 will not work in this case.
Could you, please, add IR tests for these nodes?


http://reviews.llvm.org/D12479