[PATCH] D12350: FastISel: Avoid adding a successor block twice for degenerate IR.

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL246074: FastISel: Avoid adding a successor block twice for degenerate IR. (authored by matze).

Changed prior to commit:
  http://reviews.llvm.org/D12350?vs=33165&id=33243#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D12350

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/trunk/test/CodeGen/X86/fast-isel-cmp-branch.ll

Index: llvm/trunk/test/CodeGen/X86/fast-isel-cmp-branch.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-cmp-branch.ll
+++ llvm/trunk/test/CodeGen/X86/fast-isel-cmp-branch.ll
@@ -1,5 +1,18 @@
-; RUN: llc -O0 -mtriple=x86_64-linux -asm-verbose=false < %s | FileCheck %s
-; RUN: llc -O0 -mtriple=x86_64-windows-itanium -asm-verbose=false < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=x86_64-linux -asm-verbose=false -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=x86_64-windows-itanium -asm-verbose=false -verify-machineinstrs < %s | FileCheck %s
+
+; Fast-isel mustn't add a block to the MBB successor/predecessor list twice.
+; The machine verifier will catch and complain about this case.
+; CHECK-LABEL: baz
+; CHECK: retq
+define void @baz() {
+entry:
+  br i1 undef, label %exit, label %exit
+
+exit:
+  ret void
+}
+
 ; rdar://8337108
 
 ; Fast-isel shouldn't try to look through the compare because it's in a
Index: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1415,7 +1415,11 @@
   if (FuncInfo.BPI)
     BranchWeight = FuncInfo.BPI->getEdgeWeight(BranchBB,
                                                TrueMBB->getBasicBlock());
-  FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight);
+  // Add TrueMBB as successor unless it is equal to the FalseMBB: This can
+  // happen in degenerate IR and MachineIR forbids to have a block twice in the
+  // successor/predecessor lists.
+  if (TrueMBB != FalseMBB)
+    FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight);
 
   fastEmitBranch(FalseMBB, DbgLoc);
 }


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