[PATCH] D12325: Improve ISel using across lane addition reduction

[Jun Bum Lim via llvm-commits]

junbuml created this revision.
junbuml added reviewers: jmolloy, mcrosier.
junbuml added subscribers: mssimpso, bmakam, gberry, llvm-commits.

In vectorized add reduction code, the final "reduce" step is sub-optimal.
This change wll combine :
  ext  v1.16b, v0.16b, v0.16b, #8
  add  v0.4s, v1.4s, v0.4s
  dup  v1.4s, v0.s[1]
  add  v0.4s, v1.4s, v0.4s
into
  addv s0, v0.4s

This fixes PR21371.

http://reviews.llvm.org/D12325

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/aarch64-addv.ll

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