[llvm] r244503 - x86: Emit LAHF/SAHF instead of PUSHF/POPF

David Majnemer via llvm-commits llvm-commits at lists.llvm.org
Fri Aug 21 21:45:47 PDT 2015


Hi JF,

I've bisected this to PR24535, please try to take a look at it if you get a
free moment.

Given what Eli brought up, shouldn't we guard it's usage in 64-bit mode on
a -mattr flag?  Materializing lahf or sahf without knowing apriori that a
CPU can handle it seems problematic.

Thanks!

On Wed, Aug 12, 2015 at 10:59 AM, JF Bastien via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> On Wed, Aug 12, 2015 at 10:53 AM, Reid Kleckner <rnk at google.com> wrote:
>
>> On Mon, Aug 10, 2015 at 5:41 PM, Eli Friedman via llvm-commits <
>> llvm-commits at lists.llvm.org> wrote:
>>
>>> On Mon, Aug 10, 2015 at 1:59 PM, JF Bastien via llvm-commits <
>>> llvm-commits at lists.llvm.org> wrote:
>>>
>>>> Author: jfb
>>>> Date: Mon Aug 10 15:59:36 2015
>>>> New Revision: 244503
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=244503&view=rev
>>>> Log:
>>>> x86: Emit LAHF/SAHF instead of PUSHF/POPF
>>>>
>>>> NaCl's sandbox doesn't allow PUSHF/POPF out of security concerns
>>>> (priviledged emulators have forgotten to mask system bits in the past, and
>>>> EFLAGS's DF bit is a constant source of hilarity). Commit r220529 fixed
>>>> PR20376 by saving cmpxchg's flags result using EFLAGS, this commit now
>>>> generated LAHF/SAHF instead, for all of x86 (not just NaCl) because it
>>>> leads to an overall performance gain over PUSHF/POPF.
>>>>
>>>
>>> There's a problem with this: not all x86 CPUs support lahf/sahf in
>>> 64-bit mode.
>>>
>>
>> Which CPUs don't support lahf/sahf, old ones or new ones? It's basically
>> the only safe way to copy into and out of eflags.
>>
>
> Old ones:
>
> "Early AMD64 and Intel 64 CPUs lacked LAHF and SAHF instructions in
> 64-bit mode. AMD introduced these instructions (also in 64-bit mode) with
> their Athlon 64, Opteron and Turion 64 revision D processors in March 2005
> [44] <https://en.wikipedia.org/wiki/X86-64#cite_note-44>[45]
> <https://en.wikipedia.org/wiki/X86-64#cite_note-45>[46]
> <https://en.wikipedia.org/wiki/X86-64#cite_note-46> while Intel
> introduced the instructions with the Pentium 4 G1 stepping in December 2005.
> "
>  - https://en.wikipedia.org/wiki/X86-64
>
>
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