[PATCH] D12105: [ARM] Add instruction selection patterns for vmin/vmax

[silviu.baranga@arm.com via llvm-commits]

sbaranga created this revision.
sbaranga added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

The mid-end was generating vector smin/smax/umin/umax nodes, but
we were using vbsl to generatate the code. This adds the vmin/vmax
patterns and a test to check that we are now generating vmin/vmax
instructions.

http://reviews.llvm.org/D12105

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMInstrNEON.td
  test/CodeGen/ARM/minmax.ll
  test/CodeGen/ARM/vselect_imax.ll

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