[llvm] r244287 - Revert "[AArch64][FastISel] Add more truncation tests." and "[AArch64][FastISel] Always use an AND instruction when truncating to non-legal types."
Eric Christopher via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 6 15:17:13 PDT 2015
Ah, sweet. :)
-eric
On Thu, Aug 6, 2015 at 3:16 PM Juergen Ributzka <juergen at apple.com> wrote:
> Yup, will be part of the proper fix :)
>
> —Juergen
>
>
> On Aug 6, 2015, at 3:15 PM, Eric Christopher <echristo at gmail.com> wrote:
>
> Got a testcase for the revert? :)
>
> -eric
>
> On Thu, Aug 6, 2015 at 3:14 PM Juergen Ributzka via llvm-commits <
> llvm-commits at lists.llvm.org> wrote:
>
>> Author: ributzka
>> Date: Thu Aug 6 17:13:48 2015
>> New Revision: 244287
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=244287&view=rev
>> Log:
>> Revert "[AArch64][FastISel] Add more truncation tests." and
>> "[AArch64][FastISel] Always use an AND instruction when truncating to
>> non-legal types."
>>
>> This reverts commit r243198 and 243304.
>>
>> Turns out this wasn't the correct fix for this problem. It works only
>> within
>> FastISel, but fails when the truncate is selected by SDAG.
>>
>> Modified:
>> llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
>> llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
>> llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=244287&r1=244286&r2=244287&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Thu Aug 6 17:13:48
>> 2015
>> @@ -3794,34 +3794,41 @@ bool AArch64FastISel::selectTrunc(const
>> return false;
>> bool SrcIsKill = hasTrivialKill(Op);
>>
>> - // If we're truncating from i64/i32 to a smaller non-legal type then
>> generate
>> - // an AND.
>> - uint64_t Mask = 0;
>> - switch (DestVT.SimpleTy) {
>> - default:
>> - // Trunc i64 to i32 is handled by the target-independent fast-isel.
>> - return false;
>> - case MVT::i1:
>> - Mask = 0x1;
>> - break;
>> - case MVT::i8:
>> - Mask = 0xff;
>> - break;
>> - case MVT::i16:
>> - Mask = 0xffff;
>> - break;
>> - }
>> + // If we're truncating from i64 to a smaller non-legal type then
>> generate an
>> + // AND. Otherwise, we know the high bits are undefined and a truncate
>> only
>> + // generate a COPY. We cannot mark the source register also as result
>> + // register, because this can incorrectly transfer the kill flag onto
>> the
>> + // source register.
>> + unsigned ResultReg;
>> if (SrcVT == MVT::i64) {
>> + uint64_t Mask = 0;
>> + switch (DestVT.SimpleTy) {
>> + default:
>> + // Trunc i64 to i32 is handled by the target-independent fast-isel.
>> + return false;
>> + case MVT::i1:
>> + Mask = 0x1;
>> + break;
>> + case MVT::i8:
>> + Mask = 0xff;
>> + break;
>> + case MVT::i16:
>> + Mask = 0xffff;
>> + break;
>> + }
>> // Issue an extract_subreg to get the lower 32-bits.
>> - SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
>> - AArch64::sub_32);
>> - SrcIsKill = true;
>> + unsigned Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg,
>> SrcIsKill,
>> + AArch64::sub_32);
>> + // Create the AND instruction which performs the actual truncation.
>> + ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
>> + assert(ResultReg && "Unexpected AND instruction emission failure.");
>> + } else {
>> + ResultReg = createResultReg(&AArch64::GPR32RegClass);
>> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
>> + TII.get(TargetOpcode::COPY), ResultReg)
>> + .addReg(SrcReg, getKillRegState(SrcIsKill));
>> }
>>
>> - // Create the AND instruction which performs the actual truncation.
>> - unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, SrcIsKill, Mask);
>> - assert(ResultReg && "Unexpected AND instruction emission failure.");
>> -
>> updateValueMap(I, ResultReg);
>> return true;
>> }
>>
>> Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll?rev=244287&r1=244286&r2=244287&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
>> (original)
>> +++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll Thu
>> Aug 6 17:13:48 2015
>> @@ -363,8 +363,7 @@ entry:
>> define i32 @i64_trunc_i32(i64 %a) nounwind ssp {
>> entry:
>> ; CHECK-LABEL: i64_trunc_i32
>> -; CHECK: mov [[REG:x[0-9]+]], x0
>> -; CHECK-NEXT: mov x0, [[REG]]
>> +; CHECK: mov x1, x0
>> %conv = trunc i64 %a to i32
>> ret i32 %conv
>> }
>> @@ -372,9 +371,9 @@ entry:
>> define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
>> entry:
>> ; CHECK-LABEL: i64_trunc_i16
>> -; CHECK: mov x[[REG:[0-9]+]], x0
>> -; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
>> -; CHECK-NEXT: uxth w0, [[REG2]]
>> +; CHECK: mov x[[REG:[0-9]+]], x0
>> +; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
>> +; CHECK: uxth w0, [[REG2]]
>> %conv = trunc i64 %a to i16
>> ret i16 %conv
>> }
>> @@ -382,9 +381,9 @@ entry:
>> define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
>> entry:
>> ; CHECK-LABEL: i64_trunc_i8
>> -; CHECK: mov x[[REG:[0-9]+]], x0
>> -; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0xff
>> -; CHECK-NEXT: uxtb w0, [[REG2]]
>> +; CHECK: mov x[[REG:[0-9]+]], x0
>> +; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xff
>> +; CHECK: uxtb w0, [[REG2]]
>> %conv = trunc i64 %a to i8
>> ret i8 %conv
>> }
>> @@ -392,67 +391,13 @@ entry:
>> define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
>> entry:
>> ; CHECK-LABEL: i64_trunc_i1
>> -; CHECK: mov x[[REG:[0-9]+]], x0
>> -; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0x1
>> -; CHECK-NEXT: and w0, [[REG2]], #0x1
>> +; CHECK: mov x[[REG:[0-9]+]], x0
>> +; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0x1
>> +; CHECK: and w0, [[REG2]], #0x1
>> %conv = trunc i64 %a to i1
>> ret i1 %conv
>> }
>>
>> -define zeroext i16 @i32_trunc_i16(i32 %a) nounwind ssp {
>> -entry:
>> -; CHECK-LABEL: i32_trunc_i16
>> -; CHECK: and [[REG:w[0-9]+]], w0, #0xffff
>> -; CHECK-NEXT: uxth w0, [[REG]]
>> - %conv = trunc i32 %a to i16
>> - ret i16 %conv
>> -}
>> -
>> -define zeroext i8 @i32_trunc_i8(i32 %a) nounwind ssp {
>> -entry:
>> -; CHECK-LABEL: i32_trunc_i8
>> -; CHECK: and [[REG:w[0-9]+]], w0, #0xff
>> -; CHECK-NEXT: uxtb w0, [[REG]]
>> - %conv = trunc i32 %a to i8
>> - ret i8 %conv
>> -}
>> -
>> -define zeroext i1 @i32_trunc_i1(i32 %a) nounwind ssp {
>> -entry:
>> -; CHECK-LABEL: i32_trunc_i1
>> -; CHECK: and [[REG:w[0-9]+]], w0, #0x1
>> -; CHECK-NEXT: and w0, [[REG]], #0x1
>> - %conv = trunc i32 %a to i1
>> - ret i1 %conv
>> -}
>> -
>> -define zeroext i8 @i16_trunc_i8(i16 zeroext %a) nounwind ssp {
>> -entry:
>> -; CHECK-LABEL: i16_trunc_i8
>> -; CHECK: and [[REG:w[0-9]+]], w0, #0xff
>> -; CHECK-NEXT: uxtb w0, [[REG]]
>> - %conv = trunc i16 %a to i8
>> - ret i8 %conv
>> -}
>> -
>> -define zeroext i1 @i16_trunc_i1(i16 zeroext %a) nounwind ssp {
>> -entry:
>> -; CHECK-LABEL: i16_trunc_i1
>> -; CHECK: and [[REG:w[0-9]+]], w0, #0x1
>> -; CHECK-NEXT: and w0, [[REG]], #0x1
>> - %conv = trunc i16 %a to i1
>> - ret i1 %conv
>> -}
>> -
>> -define zeroext i1 @i8_trunc_i1(i8 zeroext %a) nounwind ssp {
>> -entry:
>> -; CHECK-LABEL: i8_trunc_i1
>> -; CHECK: and [[REG:w[0-9]+]], w0, #0x1
>> -; CHECK-NEXT: and w0, [[REG]], #0x1
>> - %conv = trunc i8 %a to i1
>> - ret i1 %conv
>> -}
>> -
>> ; rdar://15101939
>> define void @stack_trunc() nounwind {
>> ; CHECK-LABEL: stack_trunc
>>
>> Modified: llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll?rev=244287&r1=244286&r2=244287&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll
>> (original)
>> +++ llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll Thu Aug
>> 6 17:13:48 2015
>> @@ -1,4 +1,4 @@
>> -; RUN: llc %s -o - -O2 -verify-machineinstrs -fast-isel=true | FileCheck
>> %s
>> +; RUN: llc %s -o - -O0 -verify-machineinstrs -fast-isel=true | FileCheck
>> %s
>>
>> target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
>> target triple = "arm64-apple-ios8.0.0"
>> @@ -7,7 +7,7 @@ target triple = "arm64-apple-ios8.0.0"
>> ; This was incorrect as %.mux isn't available in the last bb.
>>
>> ; CHECK: sxtw [[REG:x[0-9]+]]
>> -; CHECK: strh wzr, {{\[}}{{.*}}, [[REG]], lsl #1]
>> +; CHECK: strh wzr, {{\[}}[[REG]], {{.*}}, lsl #1]
>>
>> ; Function Attrs: nounwind optsize ssp
>> define void @EdgeLoop(i32 %dir, i32 %edge, i32 %width, i16* %tmp89, i32
>> %tmp136, i16 %tmp144) #0 {
>>
>>
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