[PATCH] D11800: [ARM] Reorganise and simplify thumb-1 load/store selection

[John Brawn via llvm-commits]

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By rearranging the instruction definitions in ARMInstrThumb.td, and making use of AddedComplexity in one place, we can ensure that instruction selection tries to match addressing modes in the order that simplifies the selection logic. This also makes register-offset load/store be selected when it should, as previously in many case zero-immediate-offset plus an add was selected.

Repository:
  rL LLVM

http://reviews.llvm.org/D11800

Files:
  lib/Target/ARM/ARMISelDAGToDAG.cpp
  lib/Target/ARM/ARMInstrThumb.td
  test/CodeGen/ARM/load.ll

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