[PATCH] D11428: Improve EmitLoweredSelect for contiguous pseudo CMOV instructions.

[Ahmed Bougacha]

ab accepted this revision.
ab added a comment.
This revision is now accepted and ready to land.

I'd still prefer tests with only -NEXT from the label to the ret, but this LGTM as is, thanks!

-Ahmed


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:19858
@@ +19857,3 @@
+  //
+  // when rewrting this into PHIs, we have to perform some renaming on the
+  // temps since you cannot have a PHI operand refer to a PHI result earlier
----------------
rewrting -> rewriting

================
Comment at: test/CodeGen/X86/pseudo_cmov_lower.ll:218-223
@@ +217,8 @@
+; CMOV_V8I1, CMOV_V16I1, CMOV_V32I1, or CMOV_V64I1.  Instead the selects all
+; get lowered into vector length number of selects, which all eventually turn
+; into a huge number of CMOV_GR8, which are all contiguous, so the optimization
+; kicks in as long as CMOV_GR8 is supported. I couldn't find a way to get
+; CMOV_V*I1 pseudo-opcodes to get generated.
+;
+; CHECK-LABEL: foo9:
+; CHECK: ja
----------------
If this test isn't actually testing CMOV_VNI1, should it be removed?


http://reviews.llvm.org/D11428