[PATCH] D11604: AMDGPU/SI: Add support for 32-bit immediate SMRD offsets on SI

[Matt Arsenault]

arsenm added inline comments.

================
Comment at: lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:1587-1589
@@ +1586,5 @@
+bool AMDGPUOperand::isSMRDLiteralOffset() const {
+  // 32-bit literals are only supported on CI and we only want to use them
+  // when the offset is > 8-bits.
+  return isImm() && !isUInt<8>(getImm()) && isUInt<32>(getImm());
+}
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tstellarAMD wrote:
> Are you concerned that the value 0xff will be read as SRC_LITERAL rather than the actual offset?  Because there is no way to specify SRC_LITERAL using the assembler.
Yes. My understanding was you can't use 255 because that is the same as SRC_LITERAL and both are set in the same immediate field. The meaning of 255 would then change meaning depending on SI/CI.

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Comment at: test/CodeGen/AMDGPU/smrd.ll:19
@@ -17,3 +18,3 @@
 ; GCN-LABEL: {{^}}smrd1:
-; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
+; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
----------------
tstellarAMD wrote:
> I double -checked and 32-bit immediates are only supported on CI.  I updated this test to make sure it is using the 32-bit encoding of SMRD.
Because 255 is SQ_LITERAL on CI I think it will be 64-bit there


http://reviews.llvm.org/D11604