[PATCH] D11626: AMDGPU: Set SubRegIndex size and offset

[Matt Arsenault]

arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.

 I'm not sure what reasons the comment here could have had for not setting these. Without these set, there is an assertion hit during DWARF emission.


http://reviews.llvm.org/D11626

Files:
  lib/Target/AMDGPU/AMDGPURegisterInfo.td

Index: lib/Target/AMDGPU/AMDGPURegisterInfo.td
===================================================================
--- lib/Target/AMDGPU/AMDGPURegisterInfo.td
+++ lib/Target/AMDGPU/AMDGPURegisterInfo.td
@@ -14,8 +14,7 @@
 let Namespace = "AMDGPU" in {
 
 foreach Index = 0-15 in {
-  // Indices are used in a variety of ways here, so don't set a size/offset.
-  def sub#Index : SubRegIndex<-1, -1>;
+  def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
 }
 
 def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;


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