[llvm] r243288 - MIR Serialization: Serialize the machine function's liveins.
Alex Lorenz
arphaman at gmail.com
Mon Jul 27 10:42:46 PDT 2015
Author: arphaman
Date: Mon Jul 27 12:42:45 2015
New Revision: 243288
URL: http://llvm.org/viewvc/llvm-project?rev=243288&view=rev
Log:
MIR Serialization: Serialize the machine function's liveins.
Reviewers: Duncan P. N. Exon Smith
Added:
llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir
Modified:
llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
llvm/trunk/lib/CodeGen/MIRParser/MIParser.h
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=243288&r1=243287&r2=243288&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Mon Jul 27 12:42:45 2015
@@ -116,6 +116,22 @@ template <> struct MappingTraits<Virtual
static const bool flow = true;
};
+struct MachineFunctionLiveIn {
+ StringValue Register;
+ StringValue VirtualRegister;
+};
+
+template <> struct MappingTraits<MachineFunctionLiveIn> {
+ static void mapping(IO &YamlIO, MachineFunctionLiveIn &LiveIn) {
+ YamlIO.mapRequired("reg", LiveIn.Register);
+ YamlIO.mapOptional(
+ "virtual-reg", LiveIn.VirtualRegister,
+ StringValue()); // Don't print the virtual register when it's empty.
+ }
+
+ static const bool flow = true;
+};
+
struct MachineBasicBlock {
unsigned ID;
StringValue Name;
@@ -266,6 +282,7 @@ template <> struct MappingTraits<Machine
} // end namespace yaml
} // end namespace llvm
+LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineFunctionLiveIn)
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::VirtualRegisterDefinition)
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineBasicBlock)
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineStackObject)
@@ -337,8 +354,8 @@ struct MachineFunction {
bool TracksRegLiveness = false;
bool TracksSubRegLiveness = false;
std::vector<VirtualRegisterDefinition> VirtualRegisters;
+ std::vector<MachineFunctionLiveIn> LiveIns;
// TODO: Serialize the various register masks.
- // TODO: Serialize live in registers.
// Frame information
MachineFrameInfo FrameInfo;
std::vector<FixedMachineStackObject> FixedStackObjects;
@@ -359,6 +376,7 @@ template <> struct MappingTraits<Machine
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
YamlIO.mapOptional("registers", MF.VirtualRegisters);
+ YamlIO.mapOptional("liveins", MF.LiveIns);
YamlIO.mapOptional("frameInfo", MF.FrameInfo);
YamlIO.mapOptional("fixedStack", MF.FixedStackObjects);
YamlIO.mapOptional("stack", MF.StackObjects);
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=243288&r1=243287&r2=243288&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Mon Jul 27 12:42:45 2015
@@ -98,6 +98,7 @@ public:
bool parse(MachineInstr *&MI);
bool parseMBB(MachineBasicBlock *&MBB);
bool parseNamedRegister(unsigned &Reg);
+ bool parseStandaloneVirtualRegister(unsigned &Reg);
bool parseRegister(unsigned &Reg);
bool parseRegisterFlag(unsigned &Flags);
@@ -289,6 +290,18 @@ bool MIParser::parseNamedRegister(unsign
return false;
}
+bool MIParser::parseStandaloneVirtualRegister(unsigned &Reg) {
+ lex();
+ if (Token.isNot(MIToken::VirtualRegister))
+ return error("expected a virtual register");
+ if (parseRegister(Reg))
+ return 0;
+ lex();
+ if (Token.isNot(MIToken::Eof))
+ return error("expected end of string after the register reference");
+ return false;
+}
+
static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
assert(MO.isImplicit());
return MO.isDef() ? "implicit-def" : "implicit";
@@ -843,3 +856,12 @@ bool llvm::parseNamedRegisterReference(u
SMDiagnostic &Error) {
return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseNamedRegister(Reg);
}
+
+bool llvm::parseVirtualRegisterReference(unsigned &Reg, SourceMgr &SM,
+ MachineFunction &MF, StringRef Src,
+ const PerFunctionMIParsingState &PFS,
+ const SlotMapping &IRSlots,
+ SMDiagnostic &Error) {
+ return MIParser(SM, MF, Error, Src, PFS, IRSlots)
+ .parseStandaloneVirtualRegister(Reg);
+}
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.h?rev=243288&r1=243287&r2=243288&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.h (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.h Mon Jul 27 12:42:45 2015
@@ -50,6 +50,12 @@ bool parseNamedRegisterReference(unsigne
const SlotMapping &IRSlots,
SMDiagnostic &Error);
+bool parseVirtualRegisterReference(unsigned &Reg, SourceMgr &SM,
+ MachineFunction &MF, StringRef Src,
+ const PerFunctionMIParsingState &PFS,
+ const SlotMapping &IRSlots,
+ SMDiagnostic &Error);
+
} // end namespace llvm
#endif
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=243288&r1=243287&r2=243288&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Mon Jul 27 12:42:45 2015
@@ -402,6 +402,21 @@ bool MIRParserImpl::initializeRegisterIn
RegInfo.setSimpleHint(Reg, PreferredReg);
}
}
+
+ // Parse the liveins.
+ for (const auto &LiveIn : YamlMF.LiveIns) {
+ unsigned Reg = 0;
+ if (parseNamedRegisterReference(Reg, SM, MF, LiveIn.Register.Value, PFS,
+ IRSlots, Error))
+ return error(Error, LiveIn.Register.SourceRange);
+ unsigned VReg = 0;
+ if (!LiveIn.VirtualRegister.Value.empty()) {
+ if (parseVirtualRegisterReference(
+ VReg, SM, MF, LiveIn.VirtualRegister.Value, PFS, IRSlots, Error))
+ return error(Error, LiveIn.VirtualRegister.SourceRange);
+ }
+ RegInfo.addLiveIn(Reg, VReg);
+ }
return false;
}
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=243288&r1=243287&r2=243288&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Mon Jul 27 12:42:45 2015
@@ -201,6 +201,15 @@ void MIRPrinter::convert(yaml::MachineFu
printReg(PreferredReg, VReg.PreferredRegister, TRI);
MF.VirtualRegisters.push_back(VReg);
}
+
+ // Print the live ins.
+ for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
+ yaml::MachineFunctionLiveIn LiveIn;
+ printReg(I->first, LiveIn.Register, TRI);
+ if (I->second)
+ printReg(I->second, LiveIn.VirtualRegister, TRI);
+ MF.LiveIns.push_back(LiveIn);
+ }
}
void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
Added: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir?rev=243288&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir Mon Jul 27 12:42:45 2015
@@ -0,0 +1,28 @@
+# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+ define i32 @test(i32 %a) {
+ body:
+ ret i32 %a
+ }
+
+...
+---
+name: test
+isSSA: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gr32 }
+liveins:
+ # CHECK: [[@LINE+1]]:13: expected a named register
+ - { reg: '%0' }
+body:
+ - id: 0
+ name: body
+ liveins: [ '%edi' ]
+ instructions:
+ - '%0 = COPY %edi'
+ - '%eax = COPY %0'
+ - 'RETQ %eax'
+...
Added: llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir?rev=243288&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir Mon Jul 27 12:42:45 2015
@@ -0,0 +1,28 @@
+# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+ define i32 @test(i32 %a) {
+ body:
+ ret i32 %a
+ }
+
+...
+---
+name: test
+isSSA: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gr32 }
+liveins:
+ # CHECK: [[@LINE+1]]:34: expected a virtual register
+ - { reg: '%edi', virtual-reg: '%edi' }
+body:
+ - id: 0
+ name: body
+ liveins: [ '%edi' ]
+ instructions:
+ - '%0 = COPY %edi'
+ - '%eax = COPY %0'
+ - 'RETQ %eax'
+...
Added: llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir?rev=243288&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir Mon Jul 27 12:42:45 2015
@@ -0,0 +1,38 @@
+# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses machine function's liveins
+# correctly.
+
+--- |
+
+ define i32 @test(i32 %a, i32 %b) {
+ body:
+ %c = add i32 %a, %b
+ ret i32 %c
+ }
+
+...
+---
+name: test
+isSSA: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gr32 }
+ - { id: 1, class: gr32 }
+ - { id: 2, class: gr32 }
+# CHECK: liveins:
+# CHECK-NEXT: - { reg: '%edi', virtual-reg: '%0' }
+# CHECK-NEXT: - { reg: '%esi', virtual-reg: '%1' }
+liveins:
+ - { reg: '%edi', virtual-reg: '%0' }
+ - { reg: '%esi', virtual-reg: '%1' }
+body:
+ - id: 0
+ name: body
+ liveins: [ '%edi', '%esi' ]
+ instructions:
+ - '%1 = COPY %esi'
+ - '%0 = COPY %edi'
+ - '%2 = ADD32rr %0, %1, implicit-def dead %eflags'
+ - '%eax = COPY %2'
+ - 'RETQ %eax'
+...
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