[PATCH] D11524: [ARM/AArch64] Fix cost model for interleaved accesses

[silviu.baranga at arm.com]

sbaranga created this revision.
sbaranga added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

Fix the cost of interleaved accesses for ARM/AArch64.
We were calling getTypeAllocSize and using it to check
the number of bits, when we should have called
getTypeAllocSizeInBits instead.

This would pottentially cause the vectorizer to
generate loads/stores and shuffles which cannot
be matched with an interleaved access instruction.

No performance changes are expected for now since
matching/generating interleaved accesses is still
disabled by default.

http://reviews.llvm.org/D11524

Files:
  lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  lib/Target/ARM/ARMTargetTransformInfo.cpp
  test/Transforms/LoopVectorize/AArch64/interleaved_cost.ll
  test/Transforms/LoopVectorize/ARM/interleaved_cost.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D11524.30690.patch
Type: text/x-patch
Size: 5438 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20150727/a0d39fff/attachment.bin>