[PATCH] D10683: AVX-512 vector shuffle lowering
chandlerc at gmail.com
Sun Jul 26 14:08:09 PDT 2015
chandlerc added a comment.
In http://reviews.llvm.org/D10683#212179, @delena wrote:
> > You should be able to implement this like PSHUFB is handled in X86AsmPrinter::EmitInstruction.
> PSHUFBrm form loads mask from memory.
> The VPERMV and VPERMV3 sets both take mask from register. Unlike PSHUFB, they both take source operand from memory.
For PSHUFBrr forms, we work to comment the load into the register. This may already work for VPERMV and VPERMV3. You can see an example of this in vector-shuffle-128-v16.ll, @PR12412. That test shows the load of the vector constant that is used by two consecutive PSHUFB instructions.
Something that I've actually wanted to do to make these kinds of tests substantially easier to read would be to teach the instruction printer to look through trivial patterns like this. IE, walk from the register operand to its def, see if its def is a load from the constant pool, and if so, decode it into the nice shuffle syntax. Similarly, if its def is an xor of a register, decode as-if it were a zero mask. I've never had the time to go and implement it, but if this is something you're interested in, I'd love to see the patch.
Anyways, as for getting AVX-512 stuff going, if all the shuffle mask decoding logic that can be done is in place then move on to the next step. But the lack of a comment with the vector constant expanded in it in the vmovdqa64 instructions above make me think that you'll at least need to tweak the code that comments a load from a constant pool.
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