[PATCH] D11262: [SDAG] Add new ISD nodes: ISD::FMINNAN and ISD::FMAXNAN

James Molloy james at jamesmolloy.co.uk
Sun Jul 26 07:09:32 PDT 2015

Hi Hal,

Sure! This is strongly linked to my ValueTracking change. ValueTracking
will be able to identify floating point mins and maxes, but as you know
only a subset of those map to fminnum/fmaxnum. ARM at least has separate
instructions for the different NaN behavior, so the intention of these
patches is to provide SDAG support for them, and to use them most
efficiently (there are currently three separate bits of code in the
ARM/AArch64 backends to match these...).

Specifically, if matchSelectPattern() returns a SPF_FMINNUM or SPF_FMAXNUM,
  * SPNB_RETURNS_OTHER maps to ISD::FMINNUM/FMAXNUM which in ARM's case is
matched to "fminnm"/"fmaxnm".
  * SPNB_RETURNS_NAN maps to ISD::FMINNAN/FMAXNAN which in ARM's case is
matched to "fmin"/"fmax".
  * SPNB_RETURNS_ANY maps to either FMINNUM or FMINNAN depending on target
availability. In -ffast-math mode, all queries return this.

This should allow us to take advantage of target instructions as much as
possible, even in non-fast-math mode.



On Sun, 26 Jul 2015 at 01:11 hfinkel at anl.gov <hfinkel at anl.gov> wrote:

> hfinkel added a subscriber: hfinkel.
> hfinkel added a comment.
> Can you please describe the SDAG changes you have in mind; is there some
> common sequence of nodes involving fminnum/fmaxnum that you expect to turn
> into these nodes?
> Repository:
>   rL LLVM
> http://reviews.llvm.org/D11262
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> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
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